CD74HCT00E

{
  "slug": "cd74hct00e",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Logic Gates, PDIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "cd74hct00e",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cd74hct00e.kicad_sym",
    "cd74hct00e.kicad_mod",
    "cd74hct00e.glb",
    "cd74hct00e.step",
    "cd74hct00e.lbr",
    "docs/hero.png",
    "docs/cd74hct00e-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "cd74hct00e-hero.glb",
    "cd74hct00e-hero.overlay.json",
    "cd74hct00e-etched.glb"
  ],
  "component": {
    "mpn": "CD74HCT00E",
    "manufacturer": "Texas Instruments",
    "package": "PDIP-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Logic Gates",
    "datasheet": "https://www.ti.com/cn/lit/gpn/cd74hct00",
    "parts": {
      "symbol": "cd74hct00e.kicad_sym",
      "footprint": "cd74hct00e.kicad_mod",
      "model_3d": "cd74hct00e-hero.glb",
      "model_3d_plain": "cd74hct00e-etched.glb",
      "model_3d_step": "cd74hct00e-etched.step",
      "model_3d_step_plain": "cd74hct00e.step",
      "lbr": "cd74hct00e.lbr"
    },
    "distributor_links": {
      "lcsc": "C2861752",
      "digikey": "2156-CD74HCT00E-ND",
      "mouser": "595-CD74HCT00E"
    },
    "distributor_check": {
      "checked_at": "2026-10-13T15:19:47Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "2156-CD74HCT00E-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "595-CD74HCT00E",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "1A",
        "type": "input",
        "description": "Input A of gate 1; TTL-compatible CMOS input that must not be left floating, with VIL(max) 0.8 V and VIH(min) 2 V at VCC 4.5 V to 5.5 V."
      },
      {
        "number": "2",
        "name": "1B",
        "type": "input",
        "description": "Input B of gate 1; TTL-compatible CMOS input that must not be left floating, with VIL(max) 0.8 V and VIH(min) 2 V at VCC 4.5 V to 5.5 V."
      },
      {
        "number": "3",
        "name": "1Y",
        "type": "output",
        "description": "Balanced CMOS push-pull output of gate 1 (Y = A · B); unused outputs should be left disconnected."
      },
      {
        "number": "4",
        "name": "2A",
        "type": "input",
        "description": "Input A of gate 2; TTL-compatible CMOS input that must not be left floating, with VIL(max) 0.8 V and VIH(min) 2 V at VCC 4.5 V to 5.5 V."
      },
      {
        "number": "5",
        "name": "2B",
        "type": "input",
        "description": "Input B of gate 2; TTL-compatible CMOS input that must not be left floating, with VIL(max) 0.8 V and VIH(min) 2 V at VCC 4.5 V to 5.5 V."
      },
      {
        "number": "6",
        "name": "2Y",
        "type": "output",
        "description": "Balanced CMOS push-pull output of gate 2 (Y = A · B); unused outputs should be left disconnected."
      },
      {
        "number": "7",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference for the device."
      },
      {
        "number": "8",
        "name": "3Y",
        "type": "output",
        "description": "Balanced CMOS push-pull output of gate 3 (Y = A · B); unused outputs should be left disconnected."
      },
      {
        "number": "9",
        "name": "3A",
        "type": "input",
        "description": "Input A of gate 3; TTL-compatible CMOS input that must not be left floating, with VIL(max) 0.8 V and VIH(min) 2 V at VCC 4.5 V to 5.5 V."
      },
      {
        "number": "10",
        "name": "3B",
        "type": "input",
        "description": "Input B of gate 3; TTL-compatible CMOS input that must not be left floating, with VIL(max) 0.8 V and VIH(min) 2 V at VCC 4.5 V to 5.5 V."
      },
      {
        "number": "11",
        "name": "4Y",
        "type": "output",
        "description": "Balanced CMOS push-pull output of gate 4 (Y = A · B); unused outputs should be left disconnected."
      },
      {
        "number": "12",
        "name": "4A",
        "type": "input",
        "description": "Input A of gate 4; TTL-compatible CMOS input that must not be left floating, with VIL(max) 0.8 V and VIH(min) 2 V at VCC 4.5 V to 5.5 V."
      },
      {
        "number": "13",
        "name": "4B",
        "type": "input",
        "description": "Input B of gate 4; TTL-compatible CMOS input that must not be left floating, with VIL(max) 0.8 V and VIH(min) 2 V at VCC 4.5 V to 5.5 V."
      },
      {
        "number": "14",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply, 4.5 V to 5.5 V recommended operating range; a 0.1-µF bypass capacitor is recommended close to this pin."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The pin table and figure 5-1 are labelled for the D (SOIC), N (PDIP) and J (CDIP) packages together.; The datasheet gives no separate pin-type classification for the inputs and outputs beyond their func"
        ],
        "pages_sent": 25,
        "cost_usd": 0.0824,
        "at": "2026-10-13T15:19:27"
      },
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/cd74hct00",
        "pages": 25,
        "sha256": "1a0630bdef3224da",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "cd74hct00e.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "body on z = 0, through-hole leads below",
        "extents_mm": [
          7.874,
          19.05,
          6.98
        ],
        "zmin_mm": -3.3,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3dae072a95c64bee0d1e58be8e75383639f5017ab982de1749d05808a4eed058",
        "checked": "2026-10-13",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cd74hct00e-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "body on z = 0, through-hole leads below",
        "extents_mm": [
          7.874,
          19.05,
          6.98
        ],
        "zmin_mm": -3.3,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "357512b72b037052a0a31c2cc88e45b9d000cd8b6b94f4e51101bb54040c37ef",
        "checked": "2026-10-13",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}