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CD74HCT00E

Texas Instruments · Logic Gates · PDIP-14

CD74HCT00E from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	1A	input	Input A of gate 1; TTL-compatible CMOS input that must not be left floating, with VIL(max) 0.8 V and VIH(min) 2 V at VCC 4.5 V to 5.5 V.
2	1B	input	Input B of gate 1; TTL-compatible CMOS input that must not be left floating, with VIL(max) 0.8 V and VIH(min) 2 V at VCC 4.5 V to 5.5 V.
3	1Y	output	Balanced CMOS push-pull output of gate 1 (Y = A · B); unused outputs should be left disconnected.
4	2A	input	Input A of gate 2; TTL-compatible CMOS input that must not be left floating, with VIL(max) 0.8 V and VIH(min) 2 V at VCC 4.5 V to 5.5 V.
5	2B	input	Input B of gate 2; TTL-compatible CMOS input that must not be left floating, with VIL(max) 0.8 V and VIH(min) 2 V at VCC 4.5 V to 5.5 V.
6	2Y	output	Balanced CMOS push-pull output of gate 2 (Y = A · B); unused outputs should be left disconnected.
7	GND	power_in	Ground reference for the device.
8	3Y	output	Balanced CMOS push-pull output of gate 3 (Y = A · B); unused outputs should be left disconnected.
9	3A	input	Input A of gate 3; TTL-compatible CMOS input that must not be left floating, with VIL(max) 0.8 V and VIH(min) 2 V at VCC 4.5 V to 5.5 V.
10	3B	input	Input B of gate 3; TTL-compatible CMOS input that must not be left floating, with VIL(max) 0.8 V and VIH(min) 2 V at VCC 4.5 V to 5.5 V.
11	4Y	output	Balanced CMOS push-pull output of gate 4 (Y = A · B); unused outputs should be left disconnected.
12	4A	input	Input A of gate 4; TTL-compatible CMOS input that must not be left floating, with VIL(max) 0.8 V and VIH(min) 2 V at VCC 4.5 V to 5.5 V.
13	4B	input	Input B of gate 4; TTL-compatible CMOS input that must not be left floating, with VIL(max) 0.8 V and VIH(min) 2 V at VCC 4.5 V to 5.5 V.
14	VCC	power_in	Positive supply, 4.5 V to 5.5 V recommended operating range; a 0.1-µF bypass capacitor is recommended close to this pin.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	PDIP-14
Category	Logic
Pins	14

CAD (KiCad official)

Symbol: CD74HCT00E
Footprint: Package_DIP:DIP-14_W7.62mm
3D model: PDIP-14 (KiCad packages3D, STEP)
3D model files: cd74hct00e-etched.step / cd74hct00e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hct00e.step / cd74hct00e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (25 pp, sha256 1a0630bdef3224da, retrieved 2026-10-13, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF