CD74HC7046AM96

{
  "slug": "cd74hc7046am96",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
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    "clock-timing",
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  "component": {
    "mpn": "CD74HC7046AM96",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-16",
    "pin_count": 16,
    "category": "Clock/Timing",
    "subcategory": "Clock Generators, PLLs, Frequency Synthesizers",
    "datasheet": "https://www.ti.com/cn/lit/gpn/cd74hct7046a",
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    "distributor_links": {
      "lcsc": "C2866232",
      "digikey": "CD74HC7046AM96-ND",
      "mouser": "595-CD74HC7046AM96"
    },
    "distributor_check": {
      "checked_at": "2026-10-08T02:41:07Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "CD74HC7046AM96-ND",
        "status": "found",
        "lifecycle": "Active"
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        "pn": "595-CD74HC7046AM96",
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    "pins": [
      {
        "number": "1",
        "name": "LD",
        "type": "output",
        "description": "Lock Detector Output (active high) gives a HIGH level when the PLL is locked."
      },
      {
        "number": "2",
        "name": "PC1OUT",
        "type": "output",
        "description": "Phase Comparator 1 output (Exclusive-OR network) is low-pass filtered to form the VCO control voltage at DEMOUT."
      },
      {
        "number": "3",
        "name": "COMPIN",
        "type": "input",
        "description": "Comparator input receives the VCO output, either directly or through a frequency divider, and is compared with SIGIN."
      },
      {
        "number": "4",
        "name": "VCOOUT",
        "type": "output",
        "description": "VCO output has a specified duty factor of 50% and can be connected directly to COMPIN or via a frequency divider."
      },
      {
        "number": "5",
        "name": "INH",
        "type": "input",
        "description": "Inhibit input: a LOW level enables the VCO, and a HIGH level disables the VCO to minimize standby power consumption."
      },
      {
        "number": "6",
        "name": "C1A",
        "type": "passive",
        "description": "Connection A for external capacitor C1 (between C1A and C1B), which together with R1 determines the VCO frequency range."
      },
      {
        "number": "7",
        "name": "C1B",
        "type": "passive",
        "description": "Connection B for external capacitor C1 (between C1A and C1B), which together with R1 determines the VCO frequency range."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground (0V) reference; the lock detector capacitor is connected between CLD (pin 15) and this pin."
      },
      {
        "number": "9",
        "name": "VCOIN",
        "type": "input",
        "description": "VCO input has high input impedance, which simplifies low-pass filter design by not loading the filter."
      },
      {
        "number": "10",
        "name": "DEMOUT",
        "type": "output",
        "description": "Demodulator output equals the VCO input voltage; if used, a load resistor RS should be connected from DEMOUT to Gnd, and if unused it should be left open."
      },
      {
        "number": "11",
        "name": "R1",
        "type": "passive",
        "description": "Resistor R1 connection, to Gnd, which together with C1 determines the VCO frequency range."
      },
      {
        "number": "12",
        "name": "R2",
        "type": "passive",
        "description": "Resistor R2 connection, to Gnd, which enables a VCO frequency offset if required."
      },
      {
        "number": "13",
        "name": "PC2OUT",
        "type": "tri_state",
        "description": "Phase Comparator 2 three-state output of the positive edge-triggered phase and frequency detector, filtered to form the VCO control voltage."
      },
      {
        "number": "14",
        "name": "SIGIN",
        "type": "input",
        "description": "Signal input is self-biased and can be directly coupled to signals within the HC input logic levels, or capacitively coupled for smaller swings."
      },
      {
        "number": "15",
        "name": "CLD",
        "type": "passive",
        "description": "Lock detector capacitor input; the capacitor is connected between CLD and Gnd, about 1000pF for 100kHz and 10pF for 10MHz."
      },
      {
        "number": "16",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply voltage: 3V to 6V for the VCO section and 2V to 6V for the digital section."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
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        "primary_model": "claude-haiku-5-5",
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        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The page 2 TOP VIEW pinout drawing is garbled in the extracted text, so pin positions around the pac; Pin types are KiCad ERC classes inferred from the text. PC2OUT is tri_state because the datasheet de; The datasheet is an extract (8 of 29 pages). The ordering table (page 1) and package addendum (page "
        ],
        "pages_sent": 8,
        "cost_usd": 0.0636,
        "at": "2026-10-08T02:40:50"
      },
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/cd74hct7046a",
        "pages": 29,
        "sha256": "e6707ac729144ed7",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
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