component
CD74HC7046AM96
Public Made by Adomby adom
Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD74HC7046AM96
Texas Instruments · Clock Generators, PLLs, Frequency Synthesizers · SOIC-16
CD74HC7046AM96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LD | output | Lock Detector Output (active high) gives a HIGH level when the PLL is locked. |
| 2 | PC1OUT | output | Phase Comparator 1 output (Exclusive-OR network) is low-pass filtered to form the VCO control voltage at DEMOUT. |
| 3 | COMPIN | input | Comparator input receives the VCO output, either directly or through a frequency divider, and is compared with SIGIN. |
| 4 | VCOOUT | output | VCO output has a specified duty factor of 50% and can be connected directly to COMPIN or via a frequency divider. |
| 5 | INH | input | Inhibit input: a LOW level enables the VCO, and a HIGH level disables the VCO to minimize standby power consumption. |
| 6 | C1A | passive | Connection A for external capacitor C1 (between C1A and C1B), which together with R1 determines the VCO frequency range. |
| 7 | C1B | passive | Connection B for external capacitor C1 (between C1A and C1B), which together with R1 determines the VCO frequency range. |
| 8 | GND | power_in | Ground (0V) reference; the lock detector capacitor is connected between CLD (pin 15) and this pin. |
| 9 | VCOIN | input | VCO input has high input impedance, which simplifies low-pass filter design by not loading the filter. |
| 10 | DEMOUT | output | Demodulator output equals the VCO input voltage; if used, a load resistor RS should be connected from DEMOUT to Gnd, and if unused it should be left open. |
| 11 | R1 | passive | Resistor R1 connection, to Gnd, which together with C1 determines the VCO frequency range. |
| 12 | R2 | passive | Resistor R2 connection, to Gnd, which enables a VCO frequency offset if required. |
| 13 | PC2OUT | tri_state | Phase Comparator 2 three-state output of the positive edge-triggered phase and frequency detector, filtered to form the VCO control voltage. |
| 14 | SIGIN | input | Signal input is self-biased and can be directly coupled to signals within the HC input logic levels, or capacitively coupled for smaller swings. |
| 15 | CLD | passive | Lock detector capacitor input; the capacitor is connected between CLD and Gnd, about 1000pF for 100kHz and 10pF for 10MHz. |
| 16 | VCC | power_in | Positive supply voltage: 3V to 6V for the VCO section and 2V to 6V for the digital section. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Clock/Timing |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CD74HC7046AM96 - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
cd74hc7046am96-etched.step/cd74hc7046am96-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd74hc7046am96.step/cd74hc7046am96.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (29 pp, sha256
e6707ac729144ed7, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).