# CD74HC595DWR

**Texas Instruments** · Shift Registers · SOIC-16-300mil

CD74HC595DWR from Texas Instruments, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | QB | tri_state | Parallel 3-state output bit B of the storage register; high-impedance when OE is high. |
| 2 | QC | tri_state | Parallel 3-state output bit C of the storage register; high-impedance when OE is high. |
| 3 | QD | tri_state | Parallel 3-state output bit D of the storage register; high-impedance when OE is high. |
| 4 | QE | tri_state | Parallel 3-state output bit E of the storage register; high-impedance when OE is high. |
| 5 | QF | tri_state | Parallel 3-state output bit F of the storage register; high-impedance when OE is high. |
| 6 | QG | tri_state | Parallel 3-state output bit G of the storage register; high-impedance when OE is high. |
| 7 | QH | tri_state | Parallel 3-state output bit H of the storage register; high-impedance when OE is high. |
| 8 | GND | power_in | Ground reference for the device. |
| 9 | QH' | output | Serial data output from the last shift register stage, used for cascading devices; it is not 3-state. |
| 10 | SRCLR | input | Active-low shift register clear; a low level clears the shift register (asynchronous, direct overriding clear). |
| 11 | SRCLK | input | Shift register clock, positive-edge triggered; SER is shifted in on the rising edge. |
| 12 | RCLK | input | Storage register (output latch) clock, positive-edge triggered; shift register data is transferred to the outputs on the rising edge. |
| 13 | OE | input | Output enable, active low: when high, outputs QA-QH are forced to the high-impedance state. |
| 14 | SER | input | Serial data input to the 8-bit shift register; sampled on the rising edge of SRCLK, with thold of 0 ns after SRCLK at 2-6 V. |
| 15 | QA | tri_state | Parallel 3-state output bit A of the storage register; high-impedance when OE is high. |
| 16 | VCC | power_in | Supply voltage, 2 V to 6 V recommended (absolute maximum 7 V); bypass with a 0.1 µF capacitor close to the pin. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16-300mil |
| Category | Logic |
| Pins | 16 |

## CAD (KiCad official)

- Symbol: `CD74HC595DWR`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
- 3D model files: `cd74hc595dwr-etched.step` / `cd74hc595dwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74hc595dwr.step` / `cd74hc595dwr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd74hc595) (33 pp, sha256 `9ed505a61666567b`, retrieved 2026-10-08, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cd74hc595dwr-datasheet.pdf)