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CD74HC595DWR
Public Made by Adomby adom
Texas Instruments Shift Registers, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+53@@ -0,0 +1,53 @@+# CD74HC595DWR++**Texas Instruments** · Shift Registers · SOIC-16-300mil++CD74HC595DWR from Texas Instruments, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | QB | tri_state | Parallel 3-state output bit B of the storage register; high-impedance when OE is high. |+| 2 | QC | tri_state | Parallel 3-state output bit C of the storage register; high-impedance when OE is high. |+| 3 | QD | tri_state | Parallel 3-state output bit D of the storage register; high-impedance when OE is high. |+| 4 | QE | tri_state | Parallel 3-state output bit E of the storage register; high-impedance when OE is high. |+| 5 | QF | tri_state | Parallel 3-state output bit F of the storage register; high-impedance when OE is high. |+| 6 | QG | tri_state | Parallel 3-state output bit G of the storage register; high-impedance when OE is high. |+| 7 | QH | tri_state | Parallel 3-state output bit H of the storage register; high-impedance when OE is high. |+| 8 | GND | power_in | Ground reference for the device. |+| 9 | QH' | output | Serial data output from the last shift register stage, used for cascading devices; it is not 3-state. |+| 10 | SRCLR | input | Active-low shift register clear; a low level clears the shift register (asynchronous, direct overriding clear). |+| 11 | SRCLK | input | Shift register clock, positive-edge triggered; SER is shifted in on the rising edge. |+| 12 | RCLK | input | Storage register (output latch) clock, positive-edge triggered; shift register data is transferred to the outputs on the rising edge. |+| 13 | OE | input | Output enable, active low: when high, outputs QA-QH are forced to the high-impedance state. |+| 14 | SER | input | Serial data input to the 8-bit shift register; sampled on the rising edge of SRCLK, with thold of 0 ns after SRCLK at 2-6 V. |+| 15 | QA | tri_state | Parallel 3-state output bit A of the storage register; high-impedance when OE is high. |+| 16 | VCC | power_in | Supply voltage, 2 V to 6 V recommended (absolute maximum 7 V); bypass with a 0.1 µF capacitor close to the pin. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-16-300mil |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CD74HC595DWR`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16-300mil (KiCad packages3D, STEP)+- 3D model files: `cd74hc595dwr-etched.step` / `cd74hc595dwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74hc595dwr.step` / `cd74hc595dwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd74hc595) (33 pp, sha256 `9ed505a61666567b`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd74hc595dwr-datasheet.pdf)
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high-impedance when OE is high."+ },+ {+ "number": "2",+ "name": "QC",+ "type": "tri_state",+ "description": "Parallel 3-state output bit C of the storage register; high-impedance when OE is high."+ },+ {+ "number": "3",+ "name": "QD",+ "type": "tri_state",+ "description": "Parallel 3-state output bit D of the storage register; high-impedance when OE is high."+ },+ {+ "number": "4",+ "name": "QE",+ "type": "tri_state",+ "description": "Parallel 3-state output bit E of the storage register; high-impedance when OE is high."+ },+ {+ "number": "5",+ "name": "QF",+ "type": "tri_state",+ "description": "Parallel 3-state output bit F of the storage register; high-impedance when OE is high."+ },+ {+ "number": "6",+ "name": "QG",+ "type": "tri_state",+ "description": "Parallel 3-state output bit G of the storage register; high-impedance when OE is high."+ },+ {+ "number": "7",+ "name": "QH",+ "type": "tri_state",+ "description": "Parallel 3-state output bit H of the storage register; high-impedance when OE is high."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for the device."+ },+ {+ "number": "9",+ "name": "QH'",+ "type": "output",+ "description": "Serial data output from the last shift register stage, used for cascading devices; it is not 3-state."+ },+ {+ "number": "10",+ "name": "SRCLR",+ "type": "input",+ "description": "Active-low shift register clear; a low level clears the shift register (asynchronous, direct overriding clear)."+ },+ {+ "number": "11",+ "name": "SRCLK",+ "type": "input",+ "description": "Shift register clock, positive-edge triggered; SER is shifted in on the rising edge."+ },+ {+ "number": "12",+ "name": "RCLK",+ "type": "input",+ "description": "Storage register (output latch) clock, positive-edge triggered; shift register data is transferred to the outputs on the rising edge."+ },+ {+ "number": "13",+ "name": "OE",+ "type": "input",+ "description": "Output enable, active low: when high, outputs QA-QH are forced to the high-impedance state."+ },+ {+ "number": "14",+ "name": "SER",+ "type": "input",+ "description": "Serial data input to the 8-bit shift register; sampled on the rising edge of SRCLK, with thold of 0 ns after SRCLK at 2-6 V."+ },+ {+ "number": "15",+ "name": "QA",+ "type": "tri_state",+ "description": "Parallel 3-state output bit A of the storage register; high-impedance when OE is high."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage, 2 V to 6 V recommended (absolute maximum 7 V); bypass with a 0.1 µF capacitor close to the pin."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The pin-number to name mapping was reconstructed from scrambled text extraction of the pin diagram (; Output pin numbers QA–QH were taken from the scrambled pin diagram text; the standard sequence (QB=1; Datasheet gives no per-pin electrical limits beyond the device-level recommended operating condition"+ ],+ "pages_sent": 33,+ "cost_usd": 0.0941,+ "at": "2026-10-08T03:17:00"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cd74hc595",+ "pages": 33,+ "sha256": "9ed505a61666567b",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "cd74hc595dwr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "cd74hc595dwr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "8eaae4f6d30d89103b7bf6b12839195bb21ed3d7cdf1ba7dac6a173fb00942a5",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}