CD74HC32E

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  "title": "CD74HC32E",
  "brief": "Texas Instruments Logic Gates, PDIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
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    "mpn": "CD74HC32E",
    "manufacturer": "Texas Instruments",
    "package": "PDIP-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Logic Gates",
    "datasheet": "https://www.ti.com/cn/lit/gpn/cd54hc32",
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    "distributor_links": {
      "lcsc": "C2864859",
      "digikey": "2156-CD74HC32E-ND",
      "mouser": "595-CD74HC32E"
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    "pins": [
      {
        "number": "1",
        "name": "1A",
        "type": "input",
        "description": "Input A of 2-input OR gate channel 1; the gate computes Y = A + B in positive logic with standard CMOS input levels."
      },
      {
        "number": "2",
        "name": "1B",
        "type": "input",
        "description": "Input B of 2-input OR gate channel 1; the gate computes Y = A + B in positive logic with standard CMOS input levels."
      },
      {
        "number": "3",
        "name": "1Y",
        "type": "output",
        "description": "Output Y of OR gate channel 1, a balanced CMOS push-pull output that can drive up to 10 LSTTL loads."
      },
      {
        "number": "4",
        "name": "2A",
        "type": "input",
        "description": "Input A of 2-input OR gate channel 2; the gate computes Y = A + B in positive logic with standard CMOS input levels."
      },
      {
        "number": "5",
        "name": "2B",
        "type": "input",
        "description": "Input B of 2-input OR gate channel 2; the gate computes Y = A + B in positive logic with standard CMOS input levels."
      },
      {
        "number": "6",
        "name": "2Y",
        "type": "output",
        "description": "Output Y of OR gate channel 2, a balanced CMOS push-pull output that can drive up to 10 LSTTL loads."
      },
      {
        "number": "7",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference for the device; continuous current through VCC or GND is limited to ±50 mA."
      },
      {
        "number": "8",
        "name": "3Y",
        "type": "output",
        "description": "Output Y of OR gate channel 3, a balanced CMOS push-pull output that can drive up to 10 LSTTL loads."
      },
      {
        "number": "9",
        "name": "3A",
        "type": "input",
        "description": "Input A of 2-input OR gate channel 3; the gate computes Y = A + B in positive logic with standard CMOS input levels."
      },
      {
        "number": "10",
        "name": "3B",
        "type": "input",
        "description": "Input B of 2-input OR gate channel 3; the gate computes Y = A + B in positive logic with standard CMOS input levels."
      },
      {
        "number": "11",
        "name": "4Y",
        "type": "output",
        "description": "Output Y of OR gate channel 4, a balanced CMOS push-pull output that can drive up to 10 LSTTL loads."
      },
      {
        "number": "12",
        "name": "4A",
        "type": "input",
        "description": "Input A of 2-input OR gate channel 4; the gate computes Y = A + B in positive logic with standard CMOS input levels."
      },
      {
        "number": "13",
        "name": "4B",
        "type": "input",
        "description": "Input B of 2-input OR gate channel 4; the gate computes Y = A + B in positive logic with standard CMOS input levels."
      },
      {
        "number": "14",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply; the recommended supply voltage range is 2 V to 6 V (nominal 5 V)."
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          "name": "Input leakage current",
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