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CD74HC32E

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Texas Instruments Logic Gates, PDIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD74HC32E

Texas Instruments · Logic Gates · PDIP-14

CD74HC32E from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Input A of 2-input OR gate channel 1; the gate computes Y = A + B in positive logic with standard CMOS input levels.
2 1B input Input B of 2-input OR gate channel 1; the gate computes Y = A + B in positive logic with standard CMOS input levels.
3 1Y output Output Y of OR gate channel 1, a balanced CMOS push-pull output that can drive up to 10 LSTTL loads.
4 2A input Input A of 2-input OR gate channel 2; the gate computes Y = A + B in positive logic with standard CMOS input levels.
5 2B input Input B of 2-input OR gate channel 2; the gate computes Y = A + B in positive logic with standard CMOS input levels.
6 2Y output Output Y of OR gate channel 2, a balanced CMOS push-pull output that can drive up to 10 LSTTL loads.
7 GND power_in Ground reference for the device; continuous current through VCC or GND is limited to ±50 mA.
8 3Y output Output Y of OR gate channel 3, a balanced CMOS push-pull output that can drive up to 10 LSTTL loads.
9 3A input Input A of 2-input OR gate channel 3; the gate computes Y = A + B in positive logic with standard CMOS input levels.
10 3B input Input B of 2-input OR gate channel 3; the gate computes Y = A + B in positive logic with standard CMOS input levels.
11 4Y output Output Y of OR gate channel 4, a balanced CMOS push-pull output that can drive up to 10 LSTTL loads.
12 4A input Input A of 2-input OR gate channel 4; the gate computes Y = A + B in positive logic with standard CMOS input levels.
13 4B input Input B of 2-input OR gate channel 4; the gate computes Y = A + B in positive logic with standard CMOS input levels.
14 VCC power_in Positive supply; the recommended supply voltage range is 2 V to 6 V (nominal 5 V).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (absolute maximum) VCC -0.5 7 V 4
Input clamp current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
Output clamp current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 4
Continuous output current IO -25 25 mA VO > -0.5 V or VO < VCC + 0.5 V 4
Continuous current through VCC or GND -50 50 mA 4
Junction temperature, plastic package TJ 150 °C Plastic package 4
Storage temperature Tstg -65 150 °C 4
Supply voltage (recommended) VCC 2 5 6 V 4
High-level input voltage VIH 1.5 V VCC = 2 V 4
High-level input voltage VIH 3.15 V VCC = 4.5 V 4
High-level input voltage VIH 4.2 V VCC = 6 V 4
Low-level input voltage VIL 0.5 V VCC = 2 V 4
Low-level input voltage VIL 1.35 V VCC = 4.5 V 4
Low-level input voltage VIL 1.8 V VCC = 6 V 4
Input voltage VI 0 V Upper limit printed as VCC 4
Output voltage VO 0 V Upper limit printed as VCC 4
Input transition time tt 1000 ns VCC = 2 V 4
Input transition time tt 500 ns VCC = 4.5 V 4
Input transition time tt 400 ns VCC = 6 V 4
Operating free-air temperature TA -55 125 °C 4
High-level output voltage VOH 1.9 V VI = VIH or VIL; IOH = -20 µA; VCC = 2 V; TA = -55 to 125 °C column 5
High-level output voltage VOH 4.4 V VI = VIH or VIL; IOH = -20 µA; VCC = 4.5 V; TA = -55 to 125 °C column 5
High-level output voltage VOH 5.9 V VI = VIH or VIL; IOH = -20 µA; VCC = 6 V; TA = -55 to 125 °C column 5
High-level output voltage VOH 3.7 V VI = VIH or VIL; IOH = -4 mA; VCC = 4.5 V; TA = -55 to 125 °C column 5
High-level output voltage VOH 5.2 V VI = VIH or VIL; IOH = -5.2 mA; VCC = 6 V; TA = -55 to 125 °C column 5
Low-level output voltage VOL 0.1 V VI = VIH or VIL; IOL = 20 µA; VCC = 2 V; TA = -55 to 125 °C column 5
Low-level output voltage VOL 0.4 V VI = VIH or VIL; IOL = 4 mA; VCC = 4.5 V; TA = -55 to 125 °C column 5
Input leakage current II -1 1 µA VI = VCC or 0; VCC = 6 V; TA = -55 to 125 °C column (printed ±1) 5
Supply current ICC 40 µA VI = VCC or 0; IO = 0; VCC = 6 V; TA = -55 to 125 °C column 5
Propagation delay A or B to Y tpd 135 ns CL = 50 pF; VCC = 2 V; TA = -55 to 125 °C column 5
Propagation delay A or B to Y tpd 27 ns CL = 50 pF; VCC = 4.5 V; TA = -55 to 125 °C column 5
Propagation delay A or B to Y tpd 23 ns CL = 50 pF; VCC = 6 V; TA = -55 to 125 °C column 5
Transition time Y tt 110 ns CL = 50 pF; VCC = 2 V; TA = -55 to 125 °C column 6
Transition time Y tt 22 ns CL = 50 pF; VCC = 4.5 V; TA = -55 to 125 °C column 6
Transition time Y tt 19 ns CL = 50 pF; VCC = 6 V; TA = -55 to 125 °C column 6
Input capacitance Ci 10 pF VCC = 5 V 5
Junction-to-ambient thermal resistance (N, PDIP-14) RθJA 64.7 °C/W N (PDIP) 14-pin package 5
Junction-to-case (top) thermal resistance (N, PDIP-14) RθJC(top) 52.4 °C/W N (PDIP) 14-pin package 5
Junction-to-board thermal resistance (N, PDIP-14) RθJB 44.4 °C/W N (PDIP) 14-pin package 5
Junction-to-top characterization parameter (N, PDIP-14) ΨJT 32 °C/W N (PDIP) 14-pin package 5
Junction-to-board characterization parameter (N, PDIP-14) ΨJB 44.2 °C/W N (PDIP) 14-pin package 5

CAD (KiCad official)

  • Symbol: CD74HC32E
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: PDIP-14 (KiCad packages3D, STEP)
  • 3D model files: cd74hc32e-etched.step / cd74hc32e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc32e.step / cd74hc32e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (26 pp, sha256 8f5b554dbc39ef87, retrieved 2026-10-15, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF