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CD74HC240M96
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Texas Instruments Buffers, Drivers, Receivers, Transceivers, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CD74HC240M96
Texas Instruments · Buffers, Drivers, Receivers, Transceivers · SOIC-20-300mil
CD74HC240M96 from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OE | input | Active-low output enable for bank 1; when LOW, outputs 1Y0-1Y3 are enabled (inverting); when HIGH, all bank-1 outputs are high-impedance. |
| 2 | 1A0 | input | Data input A0, bank 1; drives inverting tri-state output 1Y0 when 1OE is asserted LOW; VIH min 3.15 V at VCC = 4.5 V. |
| 3 | 2Y3 | tri_state | Inverting tri-state output Y3, bank 2; enabled when 2OE is LOW; IOH = −6 mA min, VOH = 3.98 V min at VCC = 4.5 V. |
| 4 | 1A1 | input | Data input A1, bank 1; drives inverting tri-state output 1Y1 when 1OE is asserted LOW; VIH min 3.15 V at VCC = 4.5 V. |
| 5 | 2Y2 | tri_state | Inverting tri-state output Y2, bank 2; enabled when 2OE is LOW; IOH = −6 mA min, VOH = 3.98 V min at VCC = 4.5 V. |
| 6 | 1A2 | input | Data input A2, bank 1; drives inverting tri-state output 1Y2 when 1OE is asserted LOW; VIH min 3.15 V at VCC = 4.5 V. |
| 7 | 2Y1 | tri_state | Inverting tri-state output Y1, bank 2; enabled when 2OE is LOW; IOH = −6 mA min, VOH = 3.98 V min at VCC = 4.5 V. |
| 8 | 1A3 | input | Data input A3, bank 1; drives inverting tri-state output 1Y3 when 1OE is asserted LOW; VIH min 3.15 V at VCC = 4.5 V. |
| 9 | 2Y0 | tri_state | Inverting tri-state output Y0, bank 2; enabled when 2OE is LOW; IOH = −6 mA min, VOH = 3.98 V min at VCC = 4.5 V. |
| 10 | GND | power_in | Ground reference; continuous current through GND pin must not exceed ±70 mA absolute maximum. |
| 11 | 2A0 | input | Data input A0, bank 2; drives inverting tri-state output 2Y0 when 2OE is asserted LOW; VIH min 3.15 V at VCC = 4.5 V. |
| 12 | 1Y3 | tri_state | Inverting tri-state output Y3, bank 1; enabled when 1OE is LOW; IOH = −6 mA min, VOH = 3.98 V min at VCC = 4.5 V. |
| 13 | 2A1 | input | Data input A1, bank 2; drives inverting tri-state output 2Y1 when 2OE is asserted LOW; VIH min 3.15 V at VCC = 4.5 V. |
| 14 | 1Y2 | tri_state | Inverting tri-state output Y2, bank 1; enabled when 1OE is LOW; IOH = −6 mA min, VOH = 3.98 V min at VCC = 4.5 V. |
| 15 | 2A2 | input | Data input A2, bank 2; drives inverting tri-state output 2Y2 when 2OE is asserted LOW; VIH min 3.15 V at VCC = 4.5 V. |
| 16 | 1Y1 | tri_state | Inverting tri-state output Y1, bank 1; enabled when 1OE is LOW; IOH = −6 mA min, VOH = 3.98 V min at VCC = 4.5 V. |
| 17 | 2A3 | input | Data input A3, bank 2; drives inverting tri-state output 2Y3 when 2OE is asserted LOW; VIH min 3.15 V at VCC = 4.5 V. |
| 18 | 1Y0 | tri_state | Inverting tri-state output Y0, bank 1; enabled when 1OE is LOW; IOH = −6 mA min, VOH = 3.98 V min at VCC = 4.5 V. |
| 19 | 2OE | input | Active-low output enable for bank 2; when LOW, outputs 2Y0-2Y3 are enabled (inverting); when HIGH, all bank-2 outputs are high-impedance. |
| 20 | VCC | power_in | Positive supply; HC types 2 V to 6 V, HCT types 4.5 V to 5.5 V; decouple with 0.1 μF ceramic capacitor as close to pin as possible. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-20-300mil |
| Category | Logic |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
CD74HC240M96 - Footprint:
Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm - 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files:
cd74hc240m96-etched.step/cd74hc240m96-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd74hc240m96.step/cd74hc240m96.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (32 pp, sha256
cf7e141111c1576a, retrieved 2026-09-27, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-sonnet-4-6(text+vision), consensusclaude-opus-4-7(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CD74HC240M96
**Texas Instruments** · Buffers, Drivers, Receivers, Transceivers · SOIC-20-300mil
CD74HC240M96 from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OE | input | Active-low output enable for bank 1; when LOW, outputs 1Y0-1Y3 are enabled (inverting); when HIGH, all bank-1 outputs are high-impedance. |
| 2 | 1A0 | input | Data input A0, bank 1; drives inverting tri-state output 1Y0 when 1OE is asserted LOW; VIH min 3.15 V at VCC = 4.5 V. |
| 3 | 2Y3 | tri_state | Inverting tri-state output Y3, bank 2; enabled when 2OE is LOW; IOH = −6 mA min, VOH = 3.98 V min at VCC = 4.5 V. |
| 4 | 1A1 | input | Data input A1, bank 1; drives inverting tri-state output 1Y1 when 1OE is asserted LOW; VIH min 3.15 V at VCC = 4.5 V. |
| 5 | 2Y2 | tri_state | Inverting tri-state output Y2, bank 2; enabled when 2OE is LOW; IOH = −6 mA min, VOH = 3.98 V min at VCC = 4.5 V. |
| 6 | 1A2 | input | Data input A2, bank 1; drives inverting tri-state output 1Y2 when 1OE is asserted LOW; VIH min 3.15 V at VCC = 4.5 V. |
| 7 | 2Y1 | tri_state | Inverting tri-state output Y1, bank 2; enabled when 2OE is LOW; IOH = −6 mA min, VOH = 3.98 V min at VCC = 4.5 V. |
| 8 | 1A3 | input | Data input A3, bank 1; drives inverting tri-state output 1Y3 when 1OE is asserted LOW; VIH min 3.15 V at VCC = 4.5 V. |
| 9 | 2Y0 | tri_state | Inverting tri-state output Y0, bank 2; enabled when 2OE is LOW; IOH = −6 mA min, VOH = 3.98 V min at VCC = 4.5 V. |
| 10 | GND | power_in | Ground reference; continuous current through GND pin must not exceed ±70 mA absolute maximum. |
| 11 | 2A0 | input | Data input A0, bank 2; drives inverting tri-state output 2Y0 when 2OE is asserted LOW; VIH min 3.15 V at VCC = 4.5 V. |
| 12 | 1Y3 | tri_state | Inverting tri-state output Y3, bank 1; enabled when 1OE is LOW; IOH = −6 mA min, VOH = 3.98 V min at VCC = 4.5 V. |
| 13 | 2A1 | input | Data input A1, bank 2; drives inverting tri-state output 2Y1 when 2OE is asserted LOW; VIH min 3.15 V at VCC = 4.5 V. |
| 14 | 1Y2 | tri_state | Inverting tri-state output Y2, bank 1; enabled when 1OE is LOW; IOH = −6 mA min, VOH = 3.98 V min at VCC = 4.5 V. |
| 15 | 2A2 | input | Data input A2, bank 2; drives inverting tri-state output 2Y2 when 2OE is asserted LOW; VIH min 3.15 V at VCC = 4.5 V. |
| 16 | 1Y1 | tri_state | Inverting tri-state output Y1, bank 1; enabled when 1OE is LOW; IOH = −6 mA min, VOH = 3.98 V min at VCC = 4.5 V. |
| 17 | 2A3 | input | Data input A3, bank 2; drives inverting tri-state output 2Y3 when 2OE is asserted LOW; VIH min 3.15 V at VCC = 4.5 V. |
| 18 | 1Y0 | tri_state | Inverting tri-state output Y0, bank 1; enabled when 1OE is LOW; IOH = −6 mA min, VOH = 3.98 V min at VCC = 4.5 V. |
| 19 | 2OE | input | Active-low output enable for bank 2; when LOW, outputs 2Y0-2Y3 are enabled (inverting); when HIGH, all bank-2 outputs are high-impedance. |
| 20 | VCC | power_in | Positive supply; HC types 2 V to 6 V, HCT types 4.5 V to 5.5 V; decouple with 0.1 μF ceramic capacitor as close to pin as possible. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-20-300mil |
| Category | Logic |
| Pins | 20 |
## CAD (KiCad official)
- Symbol: `CD74HC240M96`
- Footprint: `Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm`
- 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files: `cd74hc240m96-etched.step` / `cd74hc240m96-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74hc240m96.step` / `cd74hc240m96.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd74hct244) (32 pp, sha256 `cf7e141111c1576a`, retrieved 2026-09-27, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-sonnet-4-6` (text+vision), consensus `claude-opus-4-7` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cd74hc240m96-datasheet.pdf)