component
CD74HC194E
Public Made by Adomby adom
Texas Instruments Shifting Register, PDIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"component": {
"mpn": "CD74HC194E",
"manufacturer": "Texas Instruments",
"package": "PDIP-16",
"pin_count": 16,
"category": "Logic ICs",
"subcategory": "Shifting Register",
"datasheet": "https://www.ti.com/lit/ds/symlink/cd74hc194e.pdf",
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"distributor_links": {
"lcsc": "C2869467",
"digikey": "2156-CD74HC194E-HC-ND",
"mouser": "595-CD74HC194E"
},
"distributor_check": {
"checked_at": "2026-10-30T17:12:41Z",
"source": "Component Ocean /api/assign-pns",
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"pn": "2156-CD74HC194E-HC-ND",
"status": "found",
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"pins": [
{
"number": "1",
"name": "MR",
"type": "input",
"description": "Asynchronous Master Reset, active low; a Low clears the register and sets Q0-Q3 low."
},
{
"number": "2",
"name": "DSR",
"type": "input",
"description": "Serial data input for shift-right mode, clocked in on the positive clock edge."
},
{
"number": "3",
"name": "D0",
"type": "input",
"description": "Parallel data input 0, loaded on the positive clock edge when S0 and S1 are high."
},
{
"number": "4",
"name": "D1",
"type": "input",
"description": "Parallel data input 1, loaded on the positive clock edge when S0 and S1 are high."
},
{
"number": "5",
"name": "D2",
"type": "input",
"description": "Parallel data input 2, loaded on the positive clock edge when S0 and S1 are high."
},
{
"number": "6",
"name": "D3",
"type": "input",
"description": "Parallel data input 3, loaded on the positive clock edge when S0 and S1 are high."
},
{
"number": "7",
"name": "DSL",
"type": "input",
"description": "Serial data input for shift-left mode, clocked in on the positive clock edge."
},
{
"number": "8",
"name": "GND",
"type": "power_in",
"description": "Ground (0V) supply pin."
},
{
"number": "9",
"name": "S0",
"type": "input",
"description": "Mode select input 0; with S1 selects hold, shift right, shift left or parallel load."
},
{
"number": "10",
"name": "S1",
"type": "input",
"description": "Mode select input 1; with S0 selects hold, shift right, shift left or parallel load."
},
{
"number": "11",
"name": "CP",
"type": "input",
"description": "Clock input; operations occur on the Low-to-High transition."
},
{
"number": "12",
"name": "Q3",
"type": "output",
"description": "Register output 3 (last stage), standard output driving 10 LSTTL loads."
},
{
"number": "13",
"name": "Q2",
"type": "output",
"description": "Register output 2, standard output driving 10 LSTTL loads."
},
{
"number": "14",
"name": "Q1",
"type": "output",
"description": "Register output 1, standard output driving 10 LSTTL loads."
},
{
"number": "15",
"name": "Q0",
"type": "output",
"description": "Register output 0 (first stage), standard output driving 10 LSTTL loads."
},
{
"number": "16",
"name": "VCC",
"type": "power_in",
"description": "Positive supply, 2V to 6V for HC types (absolute maximum -0.5V to 7V)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
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"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
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"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The page 1 pinout figure text is scrambled in extraction, so the pin-number-to-name assignments for ; VCC = 16 and GND = 8 are stated explicitly in the functional diagram text. The supply range given is; The datasheet lists PDIP (N) 16-lead as an orderable package for CD74HC194E, so the pinout applies t"
],
"pages_sent": 20,
"cost_usd": 0.0752,
"at": "2026-10-30T17:12:33"
},
"datasheet": {
"url": "https://www.ti.com/lit/ds/symlink/cd74hc194e.pdf",
"pages": 20,
"sha256": "4366a0b1e0c3c2cc",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 16,
"described": 16,
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