component
CD74HC194E
Public Made by Adomby adom
Texas Instruments Shifting Register, PDIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 2h ago |
| viewers | 2h ago |
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| cd74hc194e-etched.step | 2h ago |
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| cd74hc194e-hero.overlay.json | 2h ago |
| cd74hc194e.glb | 2h ago |
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CD74HC194E
Texas Instruments · Shifting Register · PDIP-16
CD74HC194E from Texas Instruments, in a PDIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MR | input | Asynchronous Master Reset, active low; a Low clears the register and sets Q0-Q3 low. |
| 2 | DSR | input | Serial data input for shift-right mode, clocked in on the positive clock edge. |
| 3 | D0 | input | Parallel data input 0, loaded on the positive clock edge when S0 and S1 are high. |
| 4 | D1 | input | Parallel data input 1, loaded on the positive clock edge when S0 and S1 are high. |
| 5 | D2 | input | Parallel data input 2, loaded on the positive clock edge when S0 and S1 are high. |
| 6 | D3 | input | Parallel data input 3, loaded on the positive clock edge when S0 and S1 are high. |
| 7 | DSL | input | Serial data input for shift-left mode, clocked in on the positive clock edge. |
| 8 | GND | power_in | Ground (0V) supply pin. |
| 9 | S0 | input | Mode select input 0; with S1 selects hold, shift right, shift left or parallel load. |
| 10 | S1 | input | Mode select input 1; with S0 selects hold, shift right, shift left or parallel load. |
| 11 | CP | input | Clock input; operations occur on the Low-to-High transition. |
| 12 | Q3 | output | Register output 3 (last stage), standard output driving 10 LSTTL loads. |
| 13 | Q2 | output | Register output 2, standard output driving 10 LSTTL loads. |
| 14 | Q1 | output | Register output 1, standard output driving 10 LSTTL loads. |
| 15 | Q0 | output | Register output 0 (first stage), standard output driving 10 LSTTL loads. |
| 16 | VCC | power_in | Positive supply, 2V to 6V for HC types (absolute maximum -0.5V to 7V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-16 |
| Category | Logic ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage | VCC | -0.5 | 7 | V | 3 | ||
| DC Input Diode Current | IIK | -20 | 20 | mA | For VI < -0.5V or VI > VCC + 0.5V | 3 | |
| DC Output Diode Current | IOK | -20 | 20 | mA | For VO < -0.5V or VO > VCC + 0.5V | 3 | |
| DC Output Source or Sink Current per Output Pin | IO | -25 | 25 | mA | For VO > -0.5V or VO < VCC + 0.5V | 3 | |
| DC VCC or Ground Current | ICC or IGND | -50 | 50 | mA | 3 | ||
| Maximum Storage Temperature Range | TSTG | -65 | 150 | °C | 3 | ||
| Maximum Junction Temperature | TJ | 150 | °C | 3 | |||
| Maximum Lead Temperature (Soldering 10s) | 300 | °C | Soldering 10s | 3 | |||
| Temperature Range | TA | -55 | 125 | °C | 3 | ||
| Supply Voltage Range, HC Types | VCC | 2 | 6 | V | HC types | 3 | |
| Input Rise and Fall Time 2V | 1000 | ns | VCC = 2V | 3 | |||
| Input Rise and Fall Time 4.5V | 500 | ns | VCC = 4.5V | 3 | |||
| Input Rise and Fall Time 6V | 400 | ns | VCC = 6V | 3 | |||
| Low Level Input Voltage | VIL | 1.8 | V | VCC = 6V, -55°C to 125°C | 4 | ||
| High Level Output Voltage CMOS Loads | VOH | 4.4 | V | VI = VIH or VIL, IO = -0.02mA, VCC = 4.5V, -55°C to 125°C | 4 | ||
| High Level Output Voltage TTL Loads | VOH | 3.7 | V | VI = VIH or VIL, IO = -4mA, VCC = 4.5V, -55°C to 125°C | 4 | ||
| Low Level Output Voltage CMOS Loads | VOL | 0.1 | V | VI = VIH or VIL, IO = 0.02mA, VCC = 2V, -55°C to 125°C | 3 | ||
| Low Level Output Voltage TTL Loads | VOL | 0.4 | V | VI = VIH or VIL, IO = 4mA, VCC = 4.5V, -55°C to 125°C | 3 | ||
| Input Leakage Current | II | -1 | 1 | µA | VI = VCC or GND, VCC = 6V, -55°C to 125°C | 4 | |
| Quiescent Device Current | ICC | 160 | µA | VI = VCC or GND, IO = 0, VCC = 6V, -55°C to 125°C | 4 | ||
| Max. Clock Frequency | fMAX | 4 | MHz | Figure 1, VCC = 2V, -55°C to 125°C | 5 | ||
| Max. Clock Frequency | fMAX | 20 | MHz | Figure 1, VCC = 4.5V, -55°C to 125°C | 5 | ||
| Max. Clock Frequency | fMAX | 23 | MHz | Figure 1, VCC = 6V, -55°C to 125°C | 5 | ||
| MR Pulse Width | tW | 120 | ns | Figure 2, VCC = 2V, -55°C to 125°C | 5 | ||
| MR Pulse Width | tW | 24 | ns | Figure 2, VCC = 4.5V, -55°C to 125°C | 5 | ||
| MR Pulse Width | tW | 20 | ns | Figure 2, VCC = 6V, -55°C to 125°C | 5 | ||
| Clock Pulse Width | tW | 120 | ns | Figure 1, VCC = 2V, -55°C to 125°C | 5 | ||
| Clock Pulse Width | tW | 24 | ns | Figure 1, VCC = 4.5V, -55°C to 125°C | 5 | ||
| Clock Pulse Width | tW | 20 | ns | Figure 1, VCC = 6V, -55°C to 125°C | 5 | ||
| Set-up Time Data to Clock | tSU | 105 | ns | Figure 3, VCC = 2V, -55°C to 125°C | 5 | ||
| Set-up Time Data to Clock | tSU | 21 | ns | Figure 3, VCC = 4.5V, -55°C to 125°C | 5 | ||
| Set-up Time Data to Clock | tSU | 19 | ns | Figure 3, VCC = 6V, -55°C to 125°C | 5 | ||
| Set-Up Time S1, S0 to Clock | tSU | 120 | ns | Figure 4, VCC = 2V, -55°C to 125°C | 5 | ||
| Set-Up Time S1, S0 to Clock | tSU | 24 | ns | Figure 4, VCC = 4.5V, -55°C to 125°C | 5 | ||
| Set-Up Time S1, S0 to Clock | tSU | 20 | ns | Figure 4, VCC = 6V, -55°C to 125°C | 5 | ||
| Set-up Time DSL, DSR to Clock | tSU | 105 | ns | Figure 4, VCC = 2V, -55°C to 125°C | 5 | ||
| Set-up Time DSL, DSR to Clock | tSU | 21 | ns | Figure 4, VCC = 4.5V, -55°C to 125°C | 5 | ||
| Set-up Time DSL, DSR to Clock | tSU | 18 | ns | Figure 4, VCC = 6V, -55°C to 125°C | 5 | ||
| Propagation Delay, Clock to Output | tPLH, tPHL | 265 | ns | Figure 1, CL = 50pF, VCC = 2V, input tr, tf = 6ns, -55°C to 125°C | 6 | ||
| Propagation Delay, Clock to Output | tPLH, tPHL | 53 | ns | Figure 1, CL = 50pF, VCC = 4.5V, input tr, tf = 6ns, -55°C to 125°C | 6 | ||
| Propagation Delay, Clock to Output | tPLH, tPHL | 45 | ns | Figure 1, CL = 50pF, VCC = 6V, input tr, tf = 6ns, -55°C to 125°C | 6 | ||
| Output Transition Time | tTLH, tTHL | 110 | ns | Figure 1, CL = 50pF, VCC = 2V, -55°C to 125°C | 6 | ||
| Output Transition Time | tTLH, tTHL | 22 | ns | Figure 1, CL = 50pF, VCC = 4.5V, -55°C to 125°C | 6 | ||
| Output Transition Time | tTLH, tTHL | 19 | ns | Figure 1, CL = 50pF, VCC = 6V, -55°C to 125°C | 6 | ||
| Propagation Delay, MR to Output | tPHL | 210 | ns | Figure 2, CL = 50pF, VCC = 2V, -55°C to 125°C | 6 | ||
| Propagation Delay, MR to Output | tPHL | 42 | ns | Figure 2, CL = 50pF, VCC = 4.5V, -55°C to 125°C | 6 | ||
| Propagation Delay, MR to Output | tPHL | 36 | ns | Figure 2, CL = 50pF, VCC = 6V, -55°C to 125°C | 6 | ||
| Input Capacitance | CIN | 10 | pF | -55°C to 125°C | 6 |
CAD (KiCad official)
- Symbol:
CD74HC194E - Footprint:
Package_DIP:DIP-16_W7.62mm - 3D model: PDIP-16 (KiCad packages3D, STEP)
- 3D model files:
cd74hc194e-etched.step/cd74hc194e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd74hc194e.step/cd74hc194e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (20 pp, sha256
4366a0b1e0c3c2cc, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).