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CD74HC173M96

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Texas Instruments Flip Flops, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD74HC173M96

Texas Instruments · Flip Flops · SOIC-16

CD74HC173M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE1 input Active-low three-state output enable 1; outputs go high-impedance when OE1 or OE2 (or both) is high, without affecting sequential operation.
2 OE2 input Active-low three-state output enable 2; outputs go high-impedance when OE1 or OE2 (or both) is high, without affecting sequential operation.
3 Q0 tri_state Three-state data output of flip-flop 0, changing on the positive-going clock edge and able to drive 15 LSTTL loads.
4 Q1 tri_state Three-state data output of flip-flop 1, changing on the positive-going clock edge and able to drive 15 LSTTL loads.
5 Q2 tri_state Three-state data output of flip-flop 2, changing on the positive-going clock edge and able to drive 15 LSTTL loads.
6 Q3 tri_state Three-state data output of flip-flop 3, changing on the positive-going clock edge and able to drive 15 LSTTL loads.
7 CP input Shared clock input; data outputs change on the low-to-high transition.
8 GND power_in Ground supply pin.
9 E1 input Active-low data enable 1; if either E1 or E2 is high, the flip-flops hold their present state.
10 E2 input Active-low data enable 2; if either E1 or E2 is high, the flip-flops hold their present state.
11 D3 input Data input to flip-flop 3, with 12 ns setup to clock at 4.5 V (HC, 25°C).
12 D2 input Data input to flip-flop 2, with 12 ns setup to clock at 4.5 V (HC, 25°C).
13 D1 input Data input to flip-flop 1, with 12 ns setup to clock at 4.5 V (HC, 25°C).
14 D0 input Data input to flip-flop 0, with 12 ns setup to clock at 4.5 V (HC, 25°C).
15 MR input Master reset; a logic high resets all flip-flops, forcing Q outputs low.
16 VCC power_in Supply voltage, 2 V to 6 V for HC types, with a 0.1 µF bypass capacitor recommended close to the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: CD74HC173M96
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: cd74hc173m96-etched.step / cd74hc173m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc173m96.step / cd74hc173m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (26 pp, sha256 64eda2d471cf665c, retrieved 2026-10-01, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF