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CD74HC161M96

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Texas Instruments Counters, Dividers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD74HC161M96

Texas Instruments · Counters, Dividers · SOIC-16

CD74HC161M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MR input Active-low Master Reset input; asynchronously clears all counter outputs to low for the HC161 regardless of SPE, PE, TE, or CP states; minimum MR pulse width 20 ns at VCC = 4.5 V.
2 CP input Clock Pulse input; synchronous counting and parallel presetting are accomplished on the negative-to-positive clock transition; fMAX = 30 MHz minimum at VCC = 4.5 V.
3 P0 input Parallel Data Input 0 (LSB); synchronously loaded into the counter on the rising clock edge when SPE is low; setup time to CP minimum 12 ns at VCC = 4.5 V.
4 P1 input Parallel Data Input 1; synchronously loaded into the counter on the rising clock edge when SPE is low; setup time to CP minimum 12 ns at VCC = 4.5 V.
5 P2 input Parallel Data Input 2; synchronously loaded into the counter on the rising clock edge when SPE is low; setup time to CP minimum 12 ns at VCC = 4.5 V.
6 P3 input Parallel Data Input 3 (MSB); synchronously loaded into the counter on the rising clock edge when SPE is low; setup time to CP minimum 12 ns at VCC = 4.5 V.
7 PE input Count Enable Parallel input (active high); both PE and TE must be high to enable counting; high-to-low transition should only occur while CP is high for conventional operation.
8 GND power_in Ground reference; maximum DC VCC or ground current ICC = ±50 mA.
9 SPE input Active-low Synchronous Parallel Enable input; low level disables counting and allows data at P0-P3 to be loaded into the counter synchronously on the rising clock edge; setup time to CP minimum 12 ns at VCC = 4.5 V.
10 TE input Count Enable Trickle input (active high); both TE and PE must be high to count; TE is gated with the Q outputs of all four stages such that TC goes high for one clock period at terminal count.
11 Q3 output Counter bit 3 (MSB) output; VOH ≥ 3.98 V and VOL ≤ 0.26 V at VCC = 4.5 V with TTL loads (IO = ±4 mA); propagation delay from CP maximum 37 ns at VCC = 4.5 V.
12 Q2 output Counter bit 2 output; VOH ≥ 3.98 V and VOL ≤ 0.26 V at VCC = 4.5 V with TTL loads; propagation delay from CP maximum 37 ns at VCC = 4.5 V.
13 Q1 output Counter bit 1 output; VOH ≥ 3.98 V and VOL ≤ 0.26 V at VCC = 4.5 V with TTL loads; propagation delay from CP maximum 37 ns at VCC = 4.5 V.
14 Q0 output Counter bit 0 (LSB) output; VOH ≥ 3.98 V and VOL ≤ 0.26 V at VCC = 4.5 V with TTL loads; propagation delay from CP maximum 37 ns at VCC = 4.5 V.
15 TC output Terminal Count output; goes high for one clock period when TE is high and counter is at terminal count (HHHH); used to enable the next cascaded stage via look-ahead carry.
16 VCC power_in Positive supply voltage; HC type 2 V to 6 V operating range; quiescent ICC maximum 8 µA at 25°C, 80 µA at 85°C.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: CD74HC161M96
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: cd74hc161m96-etched.step / cd74hc161m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc161m96.step / cd74hc161m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (20 pp, sha256 cfdc63695252f714, retrieved 2026-09-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF