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CD74HC161M96
Public Made by Adomby adom
Texas Instruments Counters, Dividers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# CD74HC161M96++**Texas Instruments** · Counters, Dividers · SOIC-16++CD74HC161M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | MR | input | Active-low Master Reset input; asynchronously clears all counter outputs to low for the HC161 regardless of SPE, PE, TE, or CP states; minimum MR pulse width 20 ns at VCC = 4.5 V. |+| 2 | CP | input | Clock Pulse input; synchronous counting and parallel presetting are accomplished on the negative-to-positive clock transition; fMAX = 30 MHz minimum at VCC = 4.5 V. |+| 3 | P0 | input | Parallel Data Input 0 (LSB); synchronously loaded into the counter on the rising clock edge when SPE is low; setup time to CP minimum 12 ns at VCC = 4.5 V. |+| 4 | P1 | input | Parallel Data Input 1; synchronously loaded into the counter on the rising clock edge when SPE is low; setup time to CP minimum 12 ns at VCC = 4.5 V. |+| 5 | P2 | input | Parallel Data Input 2; synchronously loaded into the counter on the rising clock edge when SPE is low; setup time to CP minimum 12 ns at VCC = 4.5 V. |+| 6 | P3 | input | Parallel Data Input 3 (MSB); synchronously loaded into the counter on the rising clock edge when SPE is low; setup time to CP minimum 12 ns at VCC = 4.5 V. |+| 7 | PE | input | Count Enable Parallel input (active high); both PE and TE must be high to enable counting; high-to-low transition should only occur while CP is high for conventional operation. |+| 8 | GND | power_in | Ground reference; maximum DC VCC or ground current ICC = ±50 mA. |+| 9 | SPE | input | Active-low Synchronous Parallel Enable input; low level disables counting and allows data at P0-P3 to be loaded into the counter synchronously on the rising clock edge; setup time to CP minimum 12 ns at VCC = 4.5 V. |+| 10 | TE | input | Count Enable Trickle input (active high); both TE and PE must be high to count; TE is gated with the Q outputs of all four stages such that TC goes high for one clock period at terminal count. |+| 11 | Q3 | output | Counter bit 3 (MSB) output; VOH ≥ 3.98 V and VOL ≤ 0.26 V at VCC = 4.5 V with TTL loads (IO = ±4 mA); propagation delay from CP maximum 37 ns at VCC = 4.5 V. |+| 12 | Q2 | output | Counter bit 2 output; VOH ≥ 3.98 V and VOL ≤ 0.26 V at VCC = 4.5 V with TTL loads; propagation delay from CP maximum 37 ns at VCC = 4.5 V. |+| 13 | Q1 | output | Counter bit 1 output; VOH ≥ 3.98 V and VOL ≤ 0.26 V at VCC = 4.5 V with TTL loads; propagation delay from CP maximum 37 ns at VCC = 4.5 V. |+| 14 | Q0 | output | Counter bit 0 (LSB) output; VOH ≥ 3.98 V and VOL ≤ 0.26 V at VCC = 4.5 V with TTL loads; propagation delay from CP maximum 37 ns at VCC = 4.5 V. |+| 15 | TC | output | Terminal Count output; goes high for one clock period when TE is high and counter is at terminal count (HHHH); used to enable the next cascaded stage via look-ahead carry. |+| 16 | VCC | power_in | Positive supply voltage; HC type 2 V to 6 V operating range; quiescent ICC maximum 8 µA at 25°C, 80 µA at 85°C. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CD74HC161M96`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)+- 3D model files: `cd74hc161m96-etched.step` / `cd74hc161m96-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd74hc161m96.step` / `cd74hc161m96.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd74hc161) (20 pp, sha256 `cfdc63695252f714`, retrieved 2026-09-27, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd74hc161m96-datasheet.pdf)
page.jsonadded+203@@ -0,0 +1,203 @@+{+ "slug": "cd74hc161m96",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Counters, Dividers, SOIC-16. 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asynchronously clears all counter outputs to low for the HC161 regardless of SPE, PE, TE, or CP states; minimum MR pulse width 20 ns at VCC = 4.5 V."+ },+ {+ "number": "2",+ "name": "CP",+ "type": "input",+ "description": "Clock Pulse input; synchronous counting and parallel presetting are accomplished on the negative-to-positive clock transition; fMAX = 30 MHz minimum at VCC = 4.5 V."+ },+ {+ "number": "3",+ "name": "P0",+ "type": "input",+ "description": "Parallel Data Input 0 (LSB); synchronously loaded into the counter on the rising clock edge when SPE is low; setup time to CP minimum 12 ns at VCC = 4.5 V."+ },+ {+ "number": "4",+ "name": "P1",+ "type": "input",+ "description": "Parallel Data Input 1; synchronously loaded into the counter on the rising clock edge when SPE is low; setup time to CP minimum 12 ns at VCC = 4.5 V."+ },+ {+ "number": "5",+ "name": "P2",+ "type": "input",+ "description": "Parallel Data Input 2; synchronously loaded into the counter on the rising clock edge when SPE is low; setup time to CP minimum 12 ns at VCC = 4.5 V."+ },+ {+ "number": "6",+ "name": "P3",+ "type": "input",+ "description": "Parallel Data Input 3 (MSB); synchronously loaded into the counter on the rising clock edge when SPE is low; setup time to CP minimum 12 ns at VCC = 4.5 V."+ },+ {+ "number": "7",+ "name": "PE",+ "type": "input",+ "description": "Count Enable Parallel input (active high); both PE and TE must be high to enable counting; high-to-low transition should only occur while CP is high for conventional operation."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference; maximum DC VCC or ground current ICC = ±50 mA."+ },+ {+ "number": "9",+ "name": "SPE",+ "type": "input",+ "description": "Active-low Synchronous Parallel Enable input; low level disables counting and allows data at P0-P3 to be loaded into the counter synchronously on the rising clock edge; setup time to CP minimum 12 ns at VCC = 4.5 V."+ },+ {+ "number": "10",+ "name": "TE",+ "type": "input",+ "description": "Count Enable Trickle input (active high); both TE and PE must be high to count; TE is gated with the Q outputs of all four stages such that TC goes high for one clock period at terminal count."+ },+ {+ "number": "11",+ "name": "Q3",+ "type": "output",+ "description": "Counter bit 3 (MSB) output; VOH ≥ 3.98 V and VOL ≤ 0.26 V at VCC = 4.5 V with TTL loads (IO = ±4 mA); propagation delay from CP maximum 37 ns at VCC = 4.5 V."+ },+ {+ "number": "12",+ "name": "Q2",+ "type": "output",+ "description": "Counter bit 2 output; VOH ≥ 3.98 V and VOL ≤ 0.26 V at VCC = 4.5 V with TTL loads; propagation delay from CP maximum 37 ns at VCC = 4.5 V."+ },+ {+ "number": "13",+ "name": "Q1",+ "type": "output",+ "description": "Counter bit 1 output; VOH ≥ 3.98 V and VOL ≤ 0.26 V at VCC = 4.5 V with TTL loads; propagation delay from CP maximum 37 ns at VCC = 4.5 V."+ },+ {+ "number": "14",+ "name": "Q0",+ "type": "output",+ "description": "Counter bit 0 (LSB) output; VOH ≥ 3.98 V and VOL ≤ 0.26 V at VCC = 4.5 V with TTL loads; propagation delay from CP maximum 37 ns at VCC = 4.5 V."+ },+ {+ "number": "15",+ "name": "TC",+ "type": "output",+ "description": "Terminal Count output; goes high for one clock period when TE is high and counter is at terminal count (HHHH); used to enable the next cascaded stage via look-ahead carry."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage; HC type 2 V to 6 V operating range; quiescent ICC maximum 8 µA at 25°C, 80 µA at 85°C."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 20,+ "cost_usd": 0.4444,+ "at": "2026-09-27T04:54:38"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cd74hc161",+ "pages": 20,+ "sha256": "cfdc63695252f714",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}