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CD5025ITS
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Shenzhen CYT Semicon Tech DC-DC Converters, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 17d ago |
| viewers | 17d ago |
| cd5025its-etched.glb | 17d ago |
| cd5025its-etched.step | 17d ago |
| cd5025its-hero.glb | 17d ago |
| cd5025its-hero.overlay.json | 17d ago |
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| cd5025its.step | 17d ago |
| package.json | 17d ago |
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| README.md | 17d ago |
CD5025ITS
Shenzhen CYT Semicon Tech · DC-DC Converters · TSSOP-16
CD5025ITS from Shenzhen CYT Semicon Tech, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Power input for the controller, specified for +13 V to +105 V (absolute maximum VIN to GND is -0.3 V to 105 V). |
| 2 | RAMP | passive | Modulator ramp signal pin whose slope is set by an external RC network from VIN, and which is discharged by an internal FET at the end of each cycle. |
| 3 | CS1 | input | Cycle-by-cycle current-limit sense input; the output enters cycle-by-cycle current limit when CS1 exceeds 0.25 V (threshold 0.22 V to 0.28 V, absolute maximum -0.3 V to 1 V). |
| 4 | CS2 | input | Soft-start current-sense input; when CS2 exceeds 0.5 V (threshold 0.45 V to 0.55 V) the outputs are disabled and soft-start begins, with the soft-start capacitor fully discharged before release at a 1 µA pull-up. |
| 5 | TIME | passive | Sets the overlap or dead time of OUT_A and OUT_B through an external RSET: a resistor to GND gives overlapping pulses, and a resistor to REF gives dead-time (out-of-phase) pulses. |
| 6 | REF | power_out | 5 V reference output (4.85 V to 5.15 V) with a maximum output current of 10 mA, requiring a 0.1 µF decoupling capacitor to ground at the pin. |
| 7 | VCC | power_out | Internal high-voltage regulator output regulated to 7.6 V (7.3 V to 7.9 V); the internal start-up regulator turns off when an auxiliary winding raises this pin above the regulation setpoint, and the recommended VCC input range is 8 V to 15 V. |
| 8 | OUT_A | output | Main switch gate driver output, capable of 3 A peak sink current. |
| 9 | OUT_B | output | Active clamp switch gate driver output, capable of 1.25 A peak sink current. |
| 10 | PGND | power_in | Power ground, connected directly to analog ground. |
| 11 | AGND | power_in | Analog ground, connected directly to power ground; for the WSON package option the exposed pad is connected to analog ground. |
| 12 | SS | passive | Soft-start control pin where an external capacitor and an internal 20 µA current source set the soft-start ramp, and the source drops to 1 µA after a CS2 overcurrent or over-temperature event. |
| 13 | COMP | input | Input pulse-width control pin that requires an external pull-up resistor when driven by an optocoupler. |
| 14 | RT | passive | Oscillator timing pin; a resistor between RT and GND sets the internal oscillator frequency (200 kHz to 240 kHz at RT = 26.7 kΩ under the test conditions). |
| 15 | SYNC | input | Oscillator synchronization input that allows the internal oscillator to lock to an external clock running 20% below its free-running frequency, with no maximum sync frequency stated. |
| 16 | UVLO | input | Line undervoltage lockout input where an external divider sets the shutdown level against a 2.5 V comparator threshold, with hysteresis from an internal 20 µA current source switched at the threshold. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Shenzhen CYT Semicon Tech |
| Package | TSSOP-16 |
| Category | Power Management (PMIC) |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC regulated output voltage | VCCReg | 7.3 | 7.6 | 7.9 | V | UVLO=3V | 4 |
| VCC load capability | IVCC-limit | 20 | 25 | mA | UVLO=3V | 4 | |
| Start-up regulator leakage current | IVIN | 165 | 500 | μA | UVLO=3V，VCC=10V | 4 | |
| VCC UVLO (rising) | VVCC_EN | 7.08 | 7.48 | V | VIN= 7V，UVLO=3V，COMP=3V | 4 | |
| VCC UVLO (falling) | VVCC_DIS | 5.08 | 6.1 | 6.9 | V | VIN= 7V，UVLO=3V，COMP=3V | 4 |
| VCC supply current | ICC | 4.2 | mA | VCC=10V，UVLO=3V，COMP=3V | 4 | ||
| Reference voltage | VREF | 4.85 | 5 | 5.15 | V | UVLO=3V | 4 |
| Cycle-by-cycle current limit threshold (CS1) | VCS1 | 0.22 | 0.25 | 0.28 | V | 4 | |
| Soft-start overcurrent threshold (CS2) | VCS2 | 0.45 | 0.5 | 0.55 | V | 4 | |
| UVLO turn-off threshold | UVLO | 2.44 | 2.5 | 2.56 | V | 4 | |
| UVLO hysteresis current when turned off | IUVLO | 16 | 20 | 24 | μA | VIN=VCC=10V，UVLO=3V，COMP悬空 | 4 |
| Soft-start charging current (SS1) | ISS1 | 17 | 22 | 27 | μA | VIN=VCC=10V，UVLO=3V，COMP悬空 | 4 |
| Soft-start charging current (SS2) | ISS2 | 0.5 | 1 | 1.5 | μA | VIN=VCC=10V，UVLO=3V，COMP悬空，CS2=1.5V | 4 |
| Pulse frequency (FOSC) | FOSC | 200 | 220 | 240 | kHz | UVLO=3V，COMP=3V | 4 |
| Maximum output pulse duty cycle | Duty(max) | 66 | 71 | 75 | % | VIN=30V，UVLO=3V，COMP=4V | 4 |
| Dead time | tdead | 75 | 105 | 135 | ns | UVLO=3V，COMP=3V | 4 |
| Overlap time | toverlap | 75 | 105 | 135 | ns | UVLO=3V，COMP=3V | 4 |
| COMP input current | ICOMP | 50 | 80 | μA | VIN=VCC=10V，UVLO=3V，COMP=4V，SS悬空 | 4 | |
| Input voltage (VIN) recommended range | 13 | 100 | V | 3 | |||
| VCC voltage recommended range | 8 | 15 | V | 3 | |||
| Operating temperature | -40 | 125 | ℃ | 3 | |||
| VIN to GND absolute maximum | -0.3 | 105 | V | 3 | |||
| VCC to GND absolute maximum | -0.3 | 16 | V | 3 | |||
| CS1, CS2 to GND absolute maximum | -0.3 | 1 | V | 3 | |||
| All other pins to GND absolute maximum | 0.3 | 7 | V | 3 |
CAD (KiCad official)
- Symbol:
CD5025ITS - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
cd5025its-etched.step/cd5025its-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd5025its.step/cd5025its.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Shenzhen CYT Semicon Tech datasheet (12 pp, sha256
74cade07119e10e0, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).