CD4572NS16ARDQ

{
  "slug": "cd4572ns16ardq",
  "version": "0.1.0",
  "type": "component",
  "description": "GR Logic Gates, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "cd4572ns16ardq",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cd4572ns16ardq.kicad_sym",
    "cd4572ns16ardq.kicad_mod",
    "cd4572ns16ardq.glb",
    "cd4572ns16ardq.step",
    "cd4572ns16ardq.lbr",
    "docs/hero.png",
    "docs/cd4572ns16ardq-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "cd4572ns16ardq-hero.glb",
    "cd4572ns16ardq-hero.overlay.json",
    "cd4572ns16ardq-etched.glb"
  ],
  "component": {
    "mpn": "CD4572NS16ARDQ",
    "manufacturer": "GR",
    "package": "SOP-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Logic Gates",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603351088141508608",
    "parts": {
      "symbol": "cd4572ns16ardq.kicad_sym",
      "footprint": "cd4572ns16ardq.kicad_mod",
      "model_3d": "cd4572ns16ardq-hero.glb",
      "model_3d_plain": "cd4572ns16ardq-etched.glb",
      "model_3d_step": "cd4572ns16ardq-etched.step",
      "model_3d_step_plain": "cd4572ns16ardq.step",
      "lbr": "cd4572ns16ardq.lbr"
    },
    "distributor_links": {
      "lcsc": "C22465477"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T18:01:53Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "OUTA",
        "type": "output",
        "description": "Inverter A output."
      },
      {
        "number": "2",
        "name": "INA",
        "type": "input",
        "description": "Inverter A input; absolute maximum input voltage is VDD+0.5 V."
      },
      {
        "number": "3",
        "name": "OUTB",
        "type": "output",
        "description": "Inverter B output."
      },
      {
        "number": "4",
        "name": "INB",
        "type": "input",
        "description": "Inverter B input; absolute maximum input voltage is VDD+0.5 V."
      },
      {
        "number": "5",
        "name": "OUTC",
        "type": "output",
        "description": "NOR gate C output."
      },
      {
        "number": "6",
        "name": "IN1C",
        "type": "input",
        "description": "NOR gate C input 1; absolute maximum input voltage is VDD+0.5 V."
      },
      {
        "number": "7",
        "name": "IN2C",
        "type": "input",
        "description": "NOR gate C input 2; this input is positioned adjacent to VSS so the gate can be used as an inverter."
      },
      {
        "number": "8",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground reference; all voltages are referenced to VSS."
      },
      {
        "number": "9",
        "name": "OUTD",
        "type": "output",
        "description": "Inverter D output."
      },
      {
        "number": "10",
        "name": "IND",
        "type": "input",
        "description": "Inverter D input; absolute maximum input voltage is VDD+0.5 V."
      },
      {
        "number": "11",
        "name": "OUTE",
        "type": "output",
        "description": "Inverter E output."
      },
      {
        "number": "12",
        "name": "INE",
        "type": "input",
        "description": "Inverter E input; absolute maximum input voltage is VDD+0.5 V."
      },
      {
        "number": "13",
        "name": "OUTF",
        "type": "output",
        "description": "NAND gate F output."
      },
      {
        "number": "14",
        "name": "IN1F",
        "type": "input",
        "description": "NAND gate F input 1; absolute maximum input voltage is VDD+0.5 V."
      },
      {
        "number": "15",
        "name": "IN2F",
        "type": "input",
        "description": "NAND gate F input 2; this input is positioned adjacent to VDD so the gate can be used as an inverter."
      },
      {
        "number": "16",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive supply; absolute maximum DC supply voltage is 20 V referenced to VSS (-0.5 V to 20 V range)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The pin table on page 2 is not labelled per package; it applies to the 16-pin device, and the orderi; The absolute-maximum input voltage row on page 3 prints the minimum as '0.5' with the sign apparentl; Output pins have no pin-specific electrical limits in the text; descriptions are functional only. Th"
        ],
        "pages_sent": 7,
        "cost_usd": 0.0287,
        "at": "2026-10-18T17:59:40"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603351088141508608",
        "pages": 7,
        "sha256": "ca281c40816409b3",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "cd4572ns16ardq.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          9.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cd4572ns16ardq-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
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          1.75
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "272894d4aea9f2ffed09d944686e1d03fa9f4e8aa14cd3021449791b52a2e8d8",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}