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Generated by kicad-footprint-generator · KiCad file format 20260206

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CD4572NS16ARDQ

GR · Logic Gates · SOP-16

CD4572NS16ARDQ from GR, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OUTA	output	Inverter A output.
2	INA	input	Inverter A input; absolute maximum input voltage is VDD+0.5 V.
3	OUTB	output	Inverter B output.
4	INB	input	Inverter B input; absolute maximum input voltage is VDD+0.5 V.
5	OUTC	output	NOR gate C output.
6	IN1C	input	NOR gate C input 1; absolute maximum input voltage is VDD+0.5 V.
7	IN2C	input	NOR gate C input 2; this input is positioned adjacent to VSS so the gate can be used as an inverter.
8	VSS	power_in	Ground reference; all voltages are referenced to VSS.
9	OUTD	output	Inverter D output.
10	IND	input	Inverter D input; absolute maximum input voltage is VDD+0.5 V.
11	OUTE	output	Inverter E output.
12	INE	input	Inverter E input; absolute maximum input voltage is VDD+0.5 V.
13	OUTF	output	NAND gate F output.
14	IN1F	input	NAND gate F input 1; absolute maximum input voltage is VDD+0.5 V.
15	IN2F	input	NAND gate F input 2; this input is positioned adjacent to VDD so the gate can be used as an inverter.
16	VDD	power_in	Positive supply; absolute maximum DC supply voltage is 20 V referenced to VSS (-0.5 V to 20 V range).

Key specifications

Parameter	Value
Manufacturer	GR
Package	SOP-16
Category	Logic
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
DC Supply Voltage Range (referenced to VSS)	VDD	-0.5		20	V	Voltage referenced to VSS terminals	3
Input Voltage Range, All Inputs	VI	0.5			V	All inputs; printed max is VDD+0.5	3
Power Dissipation	PD			500	mW		3
Junction Temperature	TJ			125	℃		3
Operating Temperature	TOP	-40		85	℃		3
Low Level Output Current	IOL	1	2		mA	VO=0.4 V; VIN=0/5 V; VDD=5 V	3
Low Level Output Current	IOL	2.5	5		mA	VO=0.5 V; VIN=0/10 V; VDD=10 V	3
Low Level Output Current	IOL	10	20		mA	VO=1.5 V; VIN=0/15 V; VDD=15 V	3
High Level Output Current	IOH	-0.5	-1		mA	VO=4.6 V; VIN=0/5 V; VDD=5 V	3
High Level Output Current	IOH	-2.5	-5		mA	VO=2.5 V; VIN=0/5 V; VDD=5 V	3
High Level Output Current	IOH	-1	-2.5		mA	VO=9.5 V; VIN=0/10 V; VDD=10 V	3
High Level Output Current	IOH	-5	-10		mA	VO=13.5 V; VIN=0/15 V; VDD=15 V	3
Low Level Output Voltage	VOL		0	0.05	V	VIN=0/5 V; VDD=5 V	3
High Level Output Voltage	VOH	4.95	5		V	VIN=0/5 V; VDD=5 V	3
High Level Output Voltage	VOH	9.95	10		V	VIN=0/10 V; VDD=10 V	3
High Level Output Voltage	VOH	14.95	15		V	VIN=0/15 V; VDD=15 V	3
Low Level Input Voltage	VIL			1	V	VO=0.5/4.5 V; VDD=5 V	3
Low Level Input Voltage	VIL			2	V	VO=1/9 V; VDD=10 V	3
Low Level Input Voltage	VIL			2.5	V	VO=1.5/13.5 V; VDD=15 V	3
High Level Input Voltage	VIH	4			V	VO=0.5/4.5 V; VDD=5 V	3
High Level Input Voltage	VIH	8			V	VO=1/9 V; VDD=10 V	3
High Level Input Voltage	VIH	12.5			V	VO=1.5/13.5 V; VDD=15 V	3
Input Leakage Current	IIN	-1	0	1	uA	VIN=0/18 V; VDD=18 V	3
Supply Current	IDD		0	1	uA	VIN=0/5 V; VDD=5 V	3

CAD (KiCad official)

Symbol: CD4572NS16ARDQ
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOP-16 (KiCad packages3D, STEP)
3D model files: cd4572ns16ardq-etched.step / cd4572ns16ardq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4572ns16ardq.step / cd4572ns16ardq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: GR datasheet (7 pp, sha256 ca281c40816409b3, retrieved 2026-10-18, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF