component

CD4520BE

Public Made by Adom

by adom

lingxingic Counters, Dividers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogiccd4520befactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 7d ago
viewers cd4520be: viewers · Ray 7d ago
cd4520be-etched.glb Publish 0.1.0 · Ray 7d ago
cd4520be-etched.step cd4520be: factory component page (tier=lcsc) · Ray 7d ago
cd4520be-hero.glb cd4520be: hero GLB from the etched model (keeps the MPN mark) · Ray 7d ago
cd4520be-hero.overlay.json Publish 0.1.0 · Ray 7d ago
cd4520be.glb Publish 0.1.0 · Ray 7d ago
cd4520be.kicad_mod Publish 0.1.0 · Ray 7d ago
cd4520be.kicad_sym Publish 0.1.0 · Ray 7d ago
cd4520be.lbr Publish 0.1.0 · Ray 7d ago
cd4520be.step Publish 0.1.0 · Ray 7d ago
package.json Publish 0.1.0 · Ray 7d ago
page.json Set visibility: public · Ray 7d ago
README.md Publish 0.1.0 · Ray 7d ago

CD4520BE

lingxingic · Counters, Dividers · DIP-16

CD4520BE from lingxingic, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CP0_1 input Clock input of counter 1 that advances the count on a LOW-to-HIGH transition (per the function table, with CP1 LOW and MR LOW).
2 CP1_1 input Clock input of counter 1 that advances the count on a HIGH-to-LOW transition (per the function table, with CP0 LOW and MR LOW).
3 Q0_1 output Output Q0 of counter 1 (bit 0); forced LOW while MR is HIGH.
4 Q1_1 output Output Q1 of counter 1 (bit 1); forced LOW while MR is HIGH.
5 Q2_1 output Output Q2 of counter 1 (bit 2); forced LOW while MR is HIGH.
6 Q3_1 output Output Q3 of counter 1 (bit 3); forced LOW while MR is HIGH.
7 MR_1 input Master reset input for counter 1; a HIGH level sets nQ0 to nQ3 LOW.
8 VSS power_in Ground supply voltage; all voltages in the datasheet are referenced to VSS (0 V).
9 CP0_2 input Clock input of counter 2 that advances the count on a LOW-to-HIGH transition (per the function table, with CP1 LOW and MR LOW).
10 CP1_2 input Clock input of counter 2 that advances the count on a HIGH-to-LOW transition (per the function table, with CP0 LOW and MR LOW).
11 Q0_2 output Output Q0 of counter 2 (bit 0); forced LOW while MR is HIGH.
12 Q1_2 output Output Q1 of counter 2 (bit 1); forced LOW while MR is HIGH.
13 Q2_2 output Output Q2 of counter 2 (bit 2); forced LOW while MR is HIGH.
14 Q3_2 output Output Q3 of counter 2 (bit 3); forced LOW while MR is HIGH.
15 MR_2 input Master reset input for counter 2; a HIGH level sets nQ0 to nQ3 LOW.
16 VDD power_in Supply voltage; recommended operating range is 3 V to 15 V, with an absolute maximum of 18 V.

Key specifications

Parameter Value
Manufacturer lingxingic
Package DIP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
IDD supply current (5V) IDD 7.5 uA VDD=5V; VI=5V or GND; IO=0A; Tamb=-40℃ to +125℃ 7
IDD supply current (10V) IDD 15 uA VDD=10V; VI=10V or GND; IO=0A; Tamb=-40℃ to +125℃ 7
IDD supply current (15V) IDD 30 uA VDD=15V; VI=15V or GND; IO=0A; Tamb=-40℃ to +125℃ 7
HIGH-level input voltage (5V) VIH 3.5 V VDD=5V; Tamb=-40℃ to +125℃ 7
HIGH-level input voltage (10V) VIH 7 V VDD=10V; Tamb=-40℃ to +125℃ 7
HIGH-level input voltage (15V) VIH 11 V VDD=15V; Tamb=-40℃ to +125℃ 7
LOW-level input voltage (5V) VIL 1.5 V VDD=5V; Tamb=-40℃ to +125℃ 7
LOW-level input voltage (10V) VIL 3 V VDD=10V; Tamb=-40℃ to +125℃ 7
LOW-level input voltage (15V) VIL 4 V VDD=15V; Tamb=-40℃ to +125℃ 7
HIGH-level output voltage (5V) VOH 4.95 V VDD=5V; /IO/<1uA; Tamb=-40℃ to +125℃ 7
HIGH-level output voltage (10V) VOH 9.95 V VDD=10V; /IO/<1uA; Tamb=-40℃ to +125℃ 7
HIGH-level output voltage (15V) VOH 14.95 V VDD=15V; /IO/<1uA; Tamb=-40℃ to +125℃ 7
LOW-level output voltage (5V) VOL 0.05 V VDD=5V; /IO/<1uA; Tamb=-40℃ to +125℃ 7
LOW-level output voltage (10V) VOL 0.05 V VDD=10V; /IO/<1uA; Tamb=-40℃ to +125℃ 7
LOW-level output voltage (15V) VOL 0.05 V VDD=15V; /IO/<1uA; Tamb=-40℃ to +125℃ 7
HIGH-level output current (5V, VO=4.6V) IOH -0.3 mA VDD=5V; VO=4.6V; Tamb=-40℃ to +125℃ 7
HIGH-level output current (5V, VO=2.5V) IOH -1.15 mA VDD=5V; VO=2.5V; Tamb=-40℃ to +125℃ 7
HIGH-level output current (10V) IOH -0.45 mA VDD=10V; VO=9.5V; Tamb=-40℃ to +125℃ 7
HIGH-level output current (15V) IOH -1.4 mA VDD=15V; VO=13.5V; Tamb=-40℃ to +125℃ 7
LOW-level output current (5V) IOL 0.29 mA VDD=5V; VO=0.4V; Tamb=-40℃ to +125℃ 7
LOW-level output current (10V) IOL 0.38 mA VDD=10V; VO=0.5V; Tamb=-40℃ to +125℃ 7
LOW-level output current (15V) IOL 1.2 mA VDD=15V; VO=1.5V; Tamb=-40℃ to +125℃ 7
input leakage current II -4 4 uA VDD=15V; VI=15V or GND; Tamb=-40℃ to +125℃ 7
supply voltage (absolute maximum) VDD -0.5 18 V 5
input voltage (absolute maximum) VI -0.5 V all inputs; max printed as VDD+0.5 V 5
DC input current (absolute maximum) IIK -10 10 mA any one input 5
storage temperature (absolute maximum) Tstg -65 150 ℃ 5
soldering temperature (absolute maximum) TL 245 ℃ 10s; DIP 5
supply voltage (recommended operating) VDD 3 15 V 5
ambient temperature (recommended operating) Tamb -40 125 ℃ in free air 5
propagation delay HIGH to LOW, nCP0/nCP1 to nQn (5V) tPHL 265 ns Tamb=-40℃ to +125℃; VDD=5V; nCP0,nCP1 to nQn; see Figure 4 9
propagation delay HIGH to LOW, nCP0/nCP1 to nQn (10V) tPHL 120 ns Tamb=-40℃ to +125℃; VDD=10V; nCP0,nCP1 to nQn; see Figure 4 9
propagation delay HIGH to LOW, nCP0/nCP1 to nQn (15V) tPHL 95 ns Tamb=-40℃ to +125℃; VDD=15V; nCP0,nCP1 to nQn; see Figure 4 9
propagation delay HIGH to LOW, nMR to nQn (5V) tPHL 180 ns Tamb=-40℃ to +125℃; VDD=5V; nMR to nQn; see Figure 4 9
propagation delay HIGH to LOW, nMR to nQn (10V) tPHL 85 ns Tamb=-40℃ to +125℃; VDD=10V; nMR to nQn; see Figure 4 9
propagation delay HIGH to LOW, nMR to nQn (15V) tPHL 60 ns Tamb=-40℃ to +125℃; VDD=15V; nMR to nQn; see Figure 4 9
propagation delay LOW to HIGH, nCP0/nCP1 to nQn (5V) tPLH 265 ns Tamb=-40℃ to +125℃; VDD=5V; nCP0,nCP1 to nQn; see Figure 4 9
propagation delay LOW to HIGH, nCP0/nCP1 to nQn (10V) tPLH 120 ns Tamb=-40℃ to +125℃; VDD=10V; nCP0,nCP1 to nQn; see Figure 4 9
propagation delay LOW to HIGH, nCP0/nCP1 to nQn (15V) tPLH 95 ns Tamb=-40℃ to +125℃; VDD=15V; nCP0,nCP1 to nQn; see Figure 4 9
transition time nQn (5V) tTHL, tTLH 145 ns Tamb=-40℃ to +125℃; VDD=5V; nQn; see Figure 4 9
transition time nQn (10V) tTHL, tTLH 72 ns Tamb=-40℃ to +125℃; VDD=10V; nQn; see Figure 4 9
transition time nQn (15V) tTHL, tTLH 48 ns Tamb=-40℃ to +125℃; VDD=15V; nQn; see Figure 4 9
recovery time nMR input (5V) trec 60 ns Tamb=-40℃ to +125℃; VDD=5V; nMR input; see Figure 5 9
recovery time nMR input (10V) trec 36 ns Tamb=-40℃ to +125℃; VDD=10V; nMR input; see Figure 5 9
recovery time nMR input (15V) trec 24 ns Tamb=-40℃ to +125℃; VDD=15V; nMR input; see Figure 5 9
set-up time nCP0 to nCP1 (5V) tsu 60 ns Tamb=-40℃ to +125℃; VDD=5V; nCP0 to nCP1; see Figure 5 9
set-up time nCP0 to nCP1 (10V) tsu 36 ns Tamb=-40℃ to +125℃; VDD=10V; nCP0 to nCP1; see Figure 5 9
set-up time nCP0 to nCP1 (15V) tsu 24 ns Tamb=-40℃ to +125℃; VDD=15V; nCP0 to nCP1; see Figure 5 9
set-up time nCP1 to nCP0 (5V) tsu 60 ns Tamb=-40℃ to +125℃; VDD=5V; nCP1 to nCP0; see Figure 5 9
set-up time nCP1 to nCP0 (10V) tsu 36 ns Tamb=-40℃ to +125℃; VDD=10V; nCP1 to nCP0; see Figure 5 9
set-up time nCP1 to nCP0 (15V) tsu 24 ns Tamb=-40℃ to +125℃; VDD=15V; nCP1 to nCP0; see Figure 5 9
maximum clock frequency fmax (5V) fmax 6 MHZ Tamb=-40℃ to +125℃; VDD=5V; nCP1, nCP0; see Figure 5 9
maximum clock frequency fmax (10V) fmax 12 MHZ Tamb=-40℃ to +125℃; VDD=10V; nCP1, nCP0; see Figure 5 9
maximum clock frequency fmax (15V) fmax 16 MHZ Tamb=-40℃ to +125℃; VDD=15V; nCP1, nCP0; see Figure 5 9

CAD (KiCad official)

  • Symbol: CD4520BE
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4520be-etched.step / cd4520be-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4520be.step / cd4520be.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (15 pp, sha256 a7eb971499055315, retrieved 2026-10-16, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF