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CD4518BDRG

Public Made by Adom

by adom

HANSCHIP semiconductor Counters, Dividers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD4518BDRG

HANSCHIP semiconductor · Counters, Dividers · SOP-16

CD4518BDRG from HANSCHIP semiconductor, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLOCK A input Clock input for counter A; counter increments on positive-going edge when ENABLE A is high, or on negative-going edge when ENABLE A is held high and clock drives the increment.
2 ENABLE A input Enable input for counter A; counter advances on positive-going CLOCK transition when ENABLE is high; hold high for single-unit clocked operation.
3 Q1A output BCD up-counter A stage-1 (LSB) output; VOL ≤ 50 mV, VOH ≥ 4.95 V at VDD = 5 V no load.
4 Q2A output BCD up-counter A stage-2 output; VOL ≤ 50 mV, VOH ≥ 4.95 V at VDD = 5 V no load.
5 Q3A output BCD up-counter A stage-3 output; VOL ≤ 50 mV, VOH ≥ 4.95 V at VDD = 5 V no load.
6 Q4A output BCD up-counter A stage-4 (MSB) output; connect to ENABLE B for ripple cascading while CLOCK B is held low.
7 RESET A input Active-high asynchronous reset for counter A; a high level forces Q1A-Q4A to logic 0; minimum reset pulse width 250 ns at VDD = 5 V.
8 VSS power_in Ground reference (0 V); all voltages referenced to this terminal.
9 CLOCK B input Clock input for counter B; counter increments on positive-going edge when ENABLE B is high; hold low for ripple cascading from Q4A.
10 ENABLE B input Enable input for counter B; counter advances on positive-going CLOCK B transition when high; used as ripple-cascade input driven by Q4A.
11 Q1B output BCD up-counter B stage-1 (LSB) output; VOL ≤ 50 mV, VOH ≥ 4.95 V at VDD = 5 V no load.
12 Q2B output BCD up-counter B stage-2 output; VOL ≤ 50 mV, VOH ≥ 4.95 V at VDD = 5 V no load.
13 Q3B output BCD up-counter B stage-3 output; VOL ≤ 50 mV, VOH ≥ 4.95 V at VDD = 5 V no load.
14 Q4B output BCD up-counter B stage-4 (MSB) output; connect to ENABLE of subsequent counter for ripple cascading.
15 RESET B input Active-high asynchronous reset for counter B; a high level forces Q1B-Q4B to logic 0; minimum reset pulse width 250 ns at VDD = 5 V.
16 VDD power_in Positive supply voltage; operating range -0.5 V to +20 V (absolute maximum); parametric ratings at 5 V, 10 V and 15 V.

Key specifications

Parameter Value
Manufacturer HANSCHIP semiconductor
Package SOP-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: CD4518BDRG
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4518bdrg-etched.step / cd4518bdrg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4518bdrg.step / cd4518bdrg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HANSCHIP semiconductor datasheet (14 pp, sha256 54370e3d6c4be386, retrieved 2026-09-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-sonnet-4-6 (text+vision), consensus claude-opus-4-7 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF