component
CD4518BDRG
Public Made by Adomby adom
HANSCHIP semiconductor Counters, Dividers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# CD4518BDRG++**HANSCHIP semiconductor** · Counters, Dividers · SOP-16++CD4518BDRG from HANSCHIP semiconductor, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CLOCK A | input | Clock input for counter A; counter increments on positive-going edge when ENABLE A is high, or on negative-going edge when ENABLE A is held high and clock drives the increment. |+| 2 | ENABLE A | input | Enable input for counter A; counter advances on positive-going CLOCK transition when ENABLE is high; hold high for single-unit clocked operation. |+| 3 | Q1A | output | BCD up-counter A stage-1 (LSB) output; VOL ≤ 50 mV, VOH ≥ 4.95 V at VDD = 5 V no load. |+| 4 | Q2A | output | BCD up-counter A stage-2 output; VOL ≤ 50 mV, VOH ≥ 4.95 V at VDD = 5 V no load. |+| 5 | Q3A | output | BCD up-counter A stage-3 output; VOL ≤ 50 mV, VOH ≥ 4.95 V at VDD = 5 V no load. |+| 6 | Q4A | output | BCD up-counter A stage-4 (MSB) output; connect to ENABLE B for ripple cascading while CLOCK B is held low. |+| 7 | RESET A | input | Active-high asynchronous reset for counter A; a high level forces Q1A-Q4A to logic 0; minimum reset pulse width 250 ns at VDD = 5 V. |+| 8 | VSS | power_in | Ground reference (0 V); all voltages referenced to this terminal. |+| 9 | CLOCK B | input | Clock input for counter B; counter increments on positive-going edge when ENABLE B is high; hold low for ripple cascading from Q4A. |+| 10 | ENABLE B | input | Enable input for counter B; counter advances on positive-going CLOCK B transition when high; used as ripple-cascade input driven by Q4A. |+| 11 | Q1B | output | BCD up-counter B stage-1 (LSB) output; VOL ≤ 50 mV, VOH ≥ 4.95 V at VDD = 5 V no load. |+| 12 | Q2B | output | BCD up-counter B stage-2 output; VOL ≤ 50 mV, VOH ≥ 4.95 V at VDD = 5 V no load. |+| 13 | Q3B | output | BCD up-counter B stage-3 output; VOL ≤ 50 mV, VOH ≥ 4.95 V at VDD = 5 V no load. |+| 14 | Q4B | output | BCD up-counter B stage-4 (MSB) output; connect to ENABLE of subsequent counter for ripple cascading. |+| 15 | RESET B | input | Active-high asynchronous reset for counter B; a high level forces Q1B-Q4B to logic 0; minimum reset pulse width 250 ns at VDD = 5 V. |+| 16 | VDD | power_in | Positive supply voltage; operating range -0.5 V to +20 V (absolute maximum); parametric ratings at 5 V, 10 V and 15 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | HANSCHIP semiconductor |+| Package | SOP-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CD4518BDRG`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOP-16 (KiCad packages3D, STEP)+- 3D model files: `cd4518bdrg-etched.step` / `cd4518bdrg-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4518bdrg.step` / `cd4518bdrg.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [HANSCHIP semiconductor datasheet](docs/cd4518bdrg-datasheet.pdf) (14 pp, sha256 `54370e3d6c4be386`, retrieved 2026-09-18, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-sonnet-4-6` (text+vision), consensus `claude-opus-4-7` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4518bdrg-datasheet.pdf)
page.jsonadded+191@@ -0,0 +1,191 @@+{+ "slug": "cd4518bdrg",+ "version": "0.1.0",+ "type": "component",+ "description": "HANSCHIP semiconductor Counters, Dividers, SOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "cd4518bdrg",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cd4518bdrg.kicad_sym",+ "cd4518bdrg.kicad_mod",+ "cd4518bdrg.glb",+ "cd4518bdrg.step",+ "cd4518bdrg.lbr",+ "docs/hero.png",+ "docs/cd4518bdrg-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "CD4518BDRG",+ "manufacturer": "HANSCHIP semiconductor",+ "package": "SOP-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Counters, Dividers",+ "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/55b07266060df0a9fb28bc8f7c257b1b.pdf",+ "parts": {+ "symbol": "cd4518bdrg.kicad_sym",+ "footprint": "cd4518bdrg.kicad_mod",+ "model_3d": "cd4518bdrg-etched.glb",+ "model_3d_plain": "cd4518bdrg.glb",+ "model_3d_step": "cd4518bdrg-etched.step",+ "model_3d_step_plain": "cd4518bdrg.step",+ "lbr": "cd4518bdrg.lbr"+ },+ "distributor_links": {+ "lcsc": "C42396709"+ },+ "pins": [+ {+ "number": "1",+ "name": "CLOCK A",+ "type": "input",+ "description": "Clock input for counter A; counter increments on positive-going edge when ENABLE A is high, or on negative-going edge when ENABLE A is held high and clock drives the increment."+ },+ {+ "number": "2",+ "name": "ENABLE A",+ "type": "input",+ "description": "Enable input for counter A; counter advances on positive-going CLOCK transition when ENABLE is high; hold high for single-unit clocked operation."+ },+ {+ "number": "3",+ "name": "Q1A",+ "type": "output",+ "description": "BCD up-counter A stage-1 (LSB) output; VOL ≤ 50 mV, VOH ≥ 4.95 V at VDD = 5 V no load."+ },+ {+ "number": "4",+ "name": "Q2A",+ "type": "output",+ "description": "BCD up-counter A stage-2 output; VOL ≤ 50 mV, VOH ≥ 4.95 V at VDD = 5 V no load."+ },+ {+ "number": "5",+ "name": "Q3A",+ "type": "output",+ "description": "BCD up-counter A stage-3 output; VOL ≤ 50 mV, VOH ≥ 4.95 V at VDD = 5 V no load."+ },+ {+ "number": "6",+ "name": "Q4A",+ "type": "output",+ "description": "BCD up-counter A stage-4 (MSB) output; connect to ENABLE B for ripple cascading while CLOCK B is held low."+ },+ {+ "number": "7",+ "name": "RESET A",+ "type": "input",+ "description": "Active-high asynchronous reset for counter A; a high level forces Q1A-Q4A to logic 0; minimum reset pulse width 250 ns at VDD = 5 V."+ },+ {+ "number": "8",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference (0 V); all voltages referenced to this terminal."+ },+ {+ "number": "9",+ "name": "CLOCK B",+ "type": "input",+ "description": "Clock input for counter B; counter increments on positive-going edge when ENABLE B is high; hold low for ripple cascading from Q4A."+ },+ {+ "number": "10",+ "name": "ENABLE B",+ "type": "input",+ "description": "Enable input for counter B; counter advances on positive-going CLOCK B transition when high; used as ripple-cascade input driven by Q4A."+ },+ {+ "number": "11",+ "name": "Q1B",+ "type": "output",+ "description": "BCD up-counter B stage-1 (LSB) output; VOL ≤ 50 mV, VOH ≥ 4.95 V at VDD = 5 V no load."+ },+ {+ "number": "12",+ "name": "Q2B",+ "type": "output",+ "description": "BCD up-counter B stage-2 output; VOL ≤ 50 mV, VOH ≥ 4.95 V at VDD = 5 V no load."+ },+ {+ "number": "13",+ "name": "Q3B",+ "type": "output",+ "description": "BCD up-counter B stage-3 output; VOL ≤ 50 mV, VOH ≥ 4.95 V at VDD = 5 V no load."+ },+ {+ "number": "14",+ "name": "Q4B",+ "type": "output",+ "description": "BCD up-counter B stage-4 (MSB) output; connect to ENABLE of subsequent counter for ripple cascading."+ },+ {+ "number": "15",+ "name": "RESET B",+ "type": "input",+ "description": "Active-high asynchronous reset for counter B; a high level forces Q1B-Q4B to logic 0; minimum reset pulse width 250 ns at VDD = 5 V."+ },+ {+ "number": "16",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply voltage; operating range -0.5 V to +20 V (absolute maximum); parametric ratings at 5 V, 10 V and 15 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-sonnet-4-6",+ "primary_mode": "text+vision",+ "consensus_model": "claude-opus-4-7",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "vision extraction: provenance cannot be text-verified; needs consensus"+ ],+ "pages_sent": 14,+ "cost_usd": 0.3855,+ "at": "2026-09-18T02:44:35"+ },+ "datasheet": {+ "url": "https://datasheet.lcsc.com/datasheet/pdf/55b07266060df0a9fb28bc8f7c257b1b.pdf",+ "pages": 14,+ "sha256": "54370e3d6c4be386",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}