CD4094BE

{
  "slug": "cd4094be",
  "version": "0.1.1",
  "type": "component",
  "description": "Texas Instruments Shift Registers, DIP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "cd4094be",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cd4094be.kicad_sym",
    "cd4094be.kicad_mod",
    "cd4094be.glb",
    "cd4094be.step",
    "cd4094be.lbr",
    "docs/hero.png",
    "docs/cd4094be-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "cd4094be-etched.glb",
    "cd4094be-etched.step",
    "cd4094be-hero.glb",
    "cd4094be-hero.overlay.json"
  ],
  "component": {
    "mpn": "CD4094BE",
    "manufacturer": "Texas Instruments",
    "package": "DIP-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Shift Registers",
    "datasheet": "https://www.ti.com/cn/lit/gpn/cd4094b",
    "parts": {
      "symbol": "cd4094be.kicad_sym",
      "footprint": "cd4094be.kicad_mod",
      "model_3d": "cd4094be-hero.glb",
      "model_3d_plain": "cd4094be-etched.glb",
      "model_3d_step": "cd4094be-etched.step",
      "model_3d_step_plain": "cd4094be.step",
      "lbr": "cd4094be.lbr"
    },
    "distributor_links": {
      "lcsc": "C88059"
    },
    "pins": [
      {
        "number": "1",
        "name": "STROBE",
        "type": "input",
        "description": "Strobe input; while high, data present in each shift-register stage is transferred to the associated storage-register (latch) stage."
      },
      {
        "number": "2",
        "name": "DATA",
        "type": "input",
        "description": "Serial data input to the first stage of the 8-stage shift register, shifted into the register on positive clock transitions."
      },
      {
        "number": "3",
        "name": "CLOCK",
        "type": "input",
        "description": "Clock input; data is shifted through the 8-stage register on positive-going clock transitions (dc to 1.25/2.5/3 MHz max at VDD=5/10/15V)."
      },
      {
        "number": "4",
        "name": "Q1",
        "type": "tri_state",
        "description": "3-state parallel buffered output of storage-register stage 1; high-impedance unless OUTPUT ENABLE is high, suitable for direct connection to common bus lines."
      },
      {
        "number": "5",
        "name": "Q2",
        "type": "tri_state",
        "description": "3-state parallel buffered output of storage-register stage 2; high-impedance unless OUTPUT ENABLE is high."
      },
      {
        "number": "6",
        "name": "Q3",
        "type": "tri_state",
        "description": "3-state parallel buffered output of storage-register stage 3; high-impedance unless OUTPUT ENABLE is high."
      },
      {
        "number": "7",
        "name": "Q4",
        "type": "tri_state",
        "description": "3-state parallel buffered output of storage-register stage 4; high-impedance unless OUTPUT ENABLE is high."
      },
      {
        "number": "8",
        "name": "VSS",
        "type": "power_in",
        "description": "Negative supply / ground reference terminal for the device; all other voltages are referenced to VSS."
      },
      {
        "number": "9",
        "name": "QS",
        "type": "output",
        "description": "Serial output, synchronous with the positive clock edge, providing data from the 8th shift-register stage for cascading multiple CD4094B devices in high-speed (fast clock rise-time) systems."
      },
      {
        "number": "10",
        "name": "Q'S",
        "type": "output",
        "description": "Serial output, synchronous with the negative clock edge; information at the positive clock edge in the 7th shift-register stage is transferred to the 8th register stage and appears here, used for cascading when clock rise time is slow."
      },
      {
        "number": "11",
        "name": "Q8",
        "type": "tri_state",
        "description": "3-state parallel buffered output of storage-register stage 8; high-impedance unless OUTPUT ENABLE is high."
      },
      {
        "number": "12",
        "name": "Q7",
        "type": "tri_state",
        "description": "3-state parallel buffered output of storage-register stage 7; high-impedance unless OUTPUT ENABLE is high."
      },
      {
        "number": "13",
        "name": "Q6",
        "type": "tri_state",
        "description": "3-state parallel buffered output of storage-register stage 6; high-impedance unless OUTPUT ENABLE is high."
      },
      {
        "number": "14",
        "name": "Q5",
        "type": "tri_state",
        "description": "3-state parallel buffered output of storage-register stage 5; high-impedance unless OUTPUT ENABLE is high."
      },
      {
        "number": "15",
        "name": "OUTPUT ENABLE",
        "type": "input",
        "description": "3-state output enable input; when high, storage-register data appears at the Q1-Q8 parallel outputs, when low the parallel outputs are open circuit (high impedance)."
      },
      {
        "number": "16",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive supply-voltage pin; recommended operating range 3V to 18V referenced to VSS (absolute maximum -0.5V to +20V)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.2",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.2",
        "primary_model": "claude-sonnet-5",
        "primary_mode": "text+vision",
        "consensus_model": "claude-opus-4-8",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "vision extraction: provenance cannot be text-verified; needs consensus"
        ],
        "pages_sent": 18,
        "cost_usd": 0.5491,
        "at": "2026-09-23T20:19:41"
      },
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/cd4094b",
        "pages": 18,
        "sha256": "52741c14b853b678",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
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      "footprint": "viewers/footprint.html"
    },
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        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "body on z = 0, through-hole leads below",
        "extents_mm": [
          7.874,
          19.177,
          6.98
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        "zmin_mm": -3.3,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "17a30b1f0ab3fd5384a1231e3c63c394888d5b952c542a8c189e023ed3467464",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
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        "role": "eda",
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        "origin": "footprint origin = pad-pattern centre",
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        "sha256": "dafcdc41b8e70f082ee940acdcb547e87c27a461e2020eb93fa24b278802bfad",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}