component
CD4094BE
Public Made by Adomby adom
Texas Instruments Shift Registers, DIP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD4094BE
Texas Instruments · Shift Registers · DIP-16
CD4094BE from Texas Instruments, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | STROBE | input | Strobe input; while high, data present in each shift-register stage is transferred to the associated storage-register (latch) stage. |
| 2 | DATA | input | Serial data input to the first stage of the 8-stage shift register, shifted into the register on positive clock transitions. |
| 3 | CLOCK | input | Clock input; data is shifted through the 8-stage register on positive-going clock transitions (dc to 1.25/2.5/3 MHz max at VDD=5/10/15V). |
| 4 | Q1 | tri_state | 3-state parallel buffered output of storage-register stage 1; high-impedance unless OUTPUT ENABLE is high, suitable for direct connection to common bus lines. |
| 5 | Q2 | tri_state | 3-state parallel buffered output of storage-register stage 2; high-impedance unless OUTPUT ENABLE is high. |
| 6 | Q3 | tri_state | 3-state parallel buffered output of storage-register stage 3; high-impedance unless OUTPUT ENABLE is high. |
| 7 | Q4 | tri_state | 3-state parallel buffered output of storage-register stage 4; high-impedance unless OUTPUT ENABLE is high. |
| 8 | VSS | power_in | Negative supply / ground reference terminal for the device; all other voltages are referenced to VSS. |
| 9 | QS | output | Serial output, synchronous with the positive clock edge, providing data from the 8th shift-register stage for cascading multiple CD4094B devices in high-speed (fast clock rise-time) systems. |
| 10 | Q'S | output | Serial output, synchronous with the negative clock edge; information at the positive clock edge in the 7th shift-register stage is transferred to the 8th register stage and appears here, used for cascading when clock rise time is slow. |
| 11 | Q8 | tri_state | 3-state parallel buffered output of storage-register stage 8; high-impedance unless OUTPUT ENABLE is high. |
| 12 | Q7 | tri_state | 3-state parallel buffered output of storage-register stage 7; high-impedance unless OUTPUT ENABLE is high. |
| 13 | Q6 | tri_state | 3-state parallel buffered output of storage-register stage 6; high-impedance unless OUTPUT ENABLE is high. |
| 14 | Q5 | tri_state | 3-state parallel buffered output of storage-register stage 5; high-impedance unless OUTPUT ENABLE is high. |
| 15 | OUTPUT ENABLE | input | 3-state output enable input; when high, storage-register data appears at the Q1-Q8 parallel outputs, when low the parallel outputs are open circuit (high impedance). |
| 16 | VDD | power_in | Positive supply-voltage pin; recommended operating range 3V to 18V referenced to VSS (absolute maximum -0.5V to +20V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | DIP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CD4094BE - Footprint:
Package_DIP:DIP-16_W7.62mm - 3D model: DIP-16 (KiCad packages3D, STEP)
- 3D model files:
cd4094be-etched.step/cd4094be-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4094be.step/cd4094be.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (18 pp, sha256
52741c14b853b678, retrieved 2026-09-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-sonnet-5(text+vision), consensusclaude-opus-4-8(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).