CD4093DMT

{
  "slug": "cd4093dmt",
  "version": "0.1.0",
  "type": "component",
  "description": "HGSEMI Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "cd4093dmt",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cd4093dmt.kicad_sym",
    "cd4093dmt.kicad_mod",
    "cd4093dmt.glb",
    "cd4093dmt.step",
    "cd4093dmt.lbr",
    "docs/hero.png",
    "docs/cd4093dmt-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "cd4093dmt-hero.glb",
    "cd4093dmt-hero.overlay.json"
  ],
  "component": {
    "mpn": "CD4093DMT",
    "manufacturer": "HGSEMI",
    "package": "TSSOP-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Logic Gates",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590923957824937984",
    "parts": {
      "symbol": "cd4093dmt.kicad_sym",
      "footprint": "cd4093dmt.kicad_mod",
      "model_3d": "cd4093dmt-hero.glb",
      "model_3d_plain": "cd4093dmt.glb",
      "model_3d_step": "cd4093dmt-etched.step",
      "model_3d_step_plain": "cd4093dmt.step",
      "lbr": "cd4093dmt.lbr"
    },
    "distributor_links": {
      "lcsc": "C20613273"
    },
    "distributor_check": {
      "checked_at": "2026-10-09T18:47:39Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "no match"
      },
      "mouser": {
        "pn": null,
        "status": "no match"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "A",
        "type": "input",
        "description": "Input A of 2-input NAND gate 1 (output J); Schmitt-trigger input with VIN limited to VSS-0.5 V to VDD+0.5 V."
      },
      {
        "number": "2",
        "name": "B",
        "type": "input",
        "description": "Input B of 2-input NAND gate 1 (output J); Schmitt-trigger input with VIN limited to VSS-0.5 V to VDD+0.5 V."
      },
      {
        "number": "3",
        "name": "J",
        "type": "output",
        "description": "Output of NAND gate 1, J = NOT(A AND B); logic high when either input is low."
      },
      {
        "number": "4",
        "name": "K",
        "type": "output",
        "description": "Output of NAND gate 2, K = NOT(C AND D); logic high when either input is low."
      },
      {
        "number": "5",
        "name": "C",
        "type": "input",
        "description": "Input C of 2-input NAND gate 2 (output K); Schmitt-trigger input with VIN limited to VSS-0.5 V to VDD+0.5 V."
      },
      {
        "number": "6",
        "name": "D",
        "type": "input",
        "description": "Input D of 2-input NAND gate 2 (output K); Schmitt-trigger input with VIN limited to VSS-0.5 V to VDD+0.5 V."
      },
      {
        "number": "7",
        "name": "VSS",
        "type": "power_in",
        "description": "Negative supply and ground reference (0 V) for the device."
      },
      {
        "number": "8",
        "name": "E",
        "type": "input",
        "description": "Input E of 2-input NAND gate 3 (output L); Schmitt-trigger input with VIN limited to VSS-0.5 V to VDD+0.5 V."
      },
      {
        "number": "9",
        "name": "F",
        "type": "input",
        "description": "Input F of 2-input NAND gate 3 (output L); Schmitt-trigger input with VIN limited to VSS-0.5 V to VDD+0.5 V."
      },
      {
        "number": "10",
        "name": "L",
        "type": "output",
        "description": "Output of NAND gate 3, L = NOT(E AND F); logic high when either input is low."
      },
      {
        "number": "11",
        "name": "M",
        "type": "output",
        "description": "Output of NAND gate 4, M = NOT(G AND H); logic high when either input is low."
      },
      {
        "number": "12",
        "name": "G",
        "type": "input",
        "description": "Input G of 2-input NAND gate 4 (output M); Schmitt-trigger input with VIN limited to VSS-0.5 V to VDD+0.5 V."
      },
      {
        "number": "13",
        "name": "H",
        "type": "input",
        "description": "Input H of 2-input NAND gate 4 (output M); Schmitt-trigger input with VIN limited to VSS-0.5 V to VDD+0.5 V."
      },
      {
        "number": "14",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive supply; absolute maximum rating is -0.5 V to 20 V, with a stated operating range of 3.0 V to 18 V."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pin table on page 2 is a single shared table for DIP-14, SOP-14 and TSSOP-14; the TSSOP-14 column is; Datasheet does not state a per-pin output current limit or pin-level function beyond the NAND logic;; Recommended operating VDD is printed as '3 15 V' in a table whose min/typ/max columns are not clearl"
        ],
        "pages_sent": 9,
        "cost_usd": 0.0416,
        "at": "2026-10-09T18:47:22"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590923957824937984",
        "pages": 9,
        "sha256": "1ecb0742a730b244",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "cd4093dmt.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          5.0,
          1.0
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3ee5786aae56190997aa793ba3cfc003fd616782770e29719b4562f012982245",
        "checked": "2026-10-09",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cd4093dmt-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          5.0,
          1.0
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "f272e885c608ef89730345d3081b1ce6c6a59496584f722d6ccf759e2bcc7a56",
        "checked": "2026-10-09",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}