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Generated by kicad-footprint-generator · KiCad file format 20260206

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cd4093dmt-etched.glb	cd4093dmt: factory component page (tier=lcsc) · Ray	13d ago
cd4093dmt-etched.step	cd4093dmt: factory component page (tier=lcsc) · Ray	13d ago
cd4093dmt-hero.glb	cd4093dmt: hero GLB from the etched model (keeps the MPN mark) · Ray	13d ago
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CD4093DMT

HGSEMI · Logic Gates · TSSOP-14

CD4093DMT from HGSEMI, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	A	input	Input A of 2-input NAND gate 1 (output J); Schmitt-trigger input with VIN limited to VSS-0.5 V to VDD+0.5 V.
2	B	input	Input B of 2-input NAND gate 1 (output J); Schmitt-trigger input with VIN limited to VSS-0.5 V to VDD+0.5 V.
3	J	output	Output of NAND gate 1, J = NOT(A AND B); logic high when either input is low.
4	K	output	Output of NAND gate 2, K = NOT(C AND D); logic high when either input is low.
5	C	input	Input C of 2-input NAND gate 2 (output K); Schmitt-trigger input with VIN limited to VSS-0.5 V to VDD+0.5 V.
6	D	input	Input D of 2-input NAND gate 2 (output K); Schmitt-trigger input with VIN limited to VSS-0.5 V to VDD+0.5 V.
7	VSS	power_in	Negative supply and ground reference (0 V) for the device.
8	E	input	Input E of 2-input NAND gate 3 (output L); Schmitt-trigger input with VIN limited to VSS-0.5 V to VDD+0.5 V.
9	F	input	Input F of 2-input NAND gate 3 (output L); Schmitt-trigger input with VIN limited to VSS-0.5 V to VDD+0.5 V.
10	L	output	Output of NAND gate 3, L = NOT(E AND F); logic high when either input is low.
11	M	output	Output of NAND gate 4, M = NOT(G AND H); logic high when either input is low.
12	G	input	Input G of 2-input NAND gate 4 (output M); Schmitt-trigger input with VIN limited to VSS-0.5 V to VDD+0.5 V.
13	H	input	Input H of 2-input NAND gate 4 (output M); Schmitt-trigger input with VIN limited to VSS-0.5 V to VDD+0.5 V.
14	VDD	power_in	Positive supply; absolute maximum rating is -0.5 V to 20 V, with a stated operating range of 3.0 V to 18 V.

Key specifications

Parameter	Value
Manufacturer	HGSEMI
Package	TSSOP-14
Category	Logic
Pins	14

CAD (KiCad official)

Symbol: CD4093DMT
Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
3D model: TSSOP-14 (KiCad packages3D, STEP)
3D model files: cd4093dmt-etched.step / cd4093dmt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4093dmt.step / cd4093dmt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: HGSEMI datasheet (9 pp, sha256 1ecb0742a730b244, retrieved 2026-10-09, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF