component

CD4071BM

Public Made by Adom

by adom

HGSEMI Gates, SOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs cd4071bm: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers cd4071bm: viewers · Ray
cd4071bm-etched.fit.json cd4071bm: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd4071bm-etched.glb cd4071bm: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd4071bm-etched.step cd4071bm: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd4071bm.glb Publish 0.1.0 · Ray
cd4071bm.kicad_mod Publish 0.1.0 · Ray
cd4071bm.kicad_sym Publish 0.1.0 · Ray
cd4071bm.lbr Publish 0.1.0 · Ray
cd4071bm.step Publish 0.1.0 · Ray
package.json Publish 0.2.0 · Ray
page.json cd4071bm: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md cd4071bm: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray

CD4071BM

HGSEMI · Gates · SOP-14

CD4071BM from HGSEMI, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Gate 1 input A. CMOS logic input, VIH >= 3.5V @ VDD=5V, VIL <= 1.5V @ VDD=5V. Input leakage <= 1uA at VDD=15V. Unused inputs must be tied to VDD or VSS.
2 1B input Gate 1 input B. CMOS logic input, VIH >= 3.5V @ VDD=5V, VIL <= 1.5V @ VDD=5V. Unused inputs must be tied to VDD or VSS.
3 1Y output Gate 1 output = 1A OR 1B. Buffered CMOS output. VOH ~ VDD, VOL ~ 0V. IOL >= 0.51 mA @ VDD=5V, VO=0.4V; IOH >= -0.51 mA @ VDD=5V, VO=4.6V.
4 2Y output Gate 2 output = 2A OR 2B. Buffered CMOS output.
5 2A input Gate 2 input A. CMOS logic input. Unused inputs must be tied to VDD or VSS.
6 2B input Gate 2 input B. CMOS logic input. Unused inputs must be tied to VDD or VSS.
7 VSS power_in Negative supply / ground reference (0 V). All input and output voltages are referenced to VSS.
8 3A input Gate 3 input A. CMOS logic input. Unused inputs must be tied to VDD or VSS.
9 3B input Gate 3 input B. CMOS logic input. Unused inputs must be tied to VDD or VSS.
10 3Y output Gate 3 output = 3A OR 3B. Buffered CMOS output.
11 4Y output Gate 4 output = 4A OR 4B. Buffered CMOS output.
12 4A input Gate 4 input A. CMOS logic input. Unused inputs must be tied to VDD or VSS.
13 4B input Gate 4 input B. CMOS logic input. Unused inputs must be tied to VDD or VSS.
14 VDD power_in Positive supply. Recommended operating range 3 V to 15 V (absolute max +18 V). Static IDD <= 5 uA @ VDD=5V, <= 15 uA @ VDD=15V.

Key specifications

Parameter Value
Manufacturer HGSEMI
Package SOP-14
Category Logic
Pins 14

Ordering variants

Same part, different packaging or reel option.

  • CD4071BM/TR
  • CD4071BMBE
  • CD4071BMBN
  • CD4071BMT/TR

CAD (KiCad official)

  • Symbol: CD4071BM
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4071bm-etched.step / cd4071bm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4071bm.step / cd4071bm.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
cd4071bm.step 195 KB You want the bare part, or you mark your own boards.
cd4071bm-etched.step 1.9 MB You want the part with CD4071BM already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 493 faces against 237 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HGSEMI datasheet (9 pp, sha256 a0af40244b85b44c, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF