component

CD4042BM

Public Made by Adom

by adom

lingxingic Latches, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs cd4042bm: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers cd4042bm: viewers · Ray
cd4042bm-etched.fit.json cd4042bm: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd4042bm-etched.glb cd4042bm: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd4042bm-etched.step cd4042bm: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd4042bm.glb Publish 0.1.0 · Ray
cd4042bm.kicad_mod Publish 0.1.0 · Ray
cd4042bm.kicad_sym Publish 0.1.0 · Ray
cd4042bm.lbr Publish 0.1.0 · Ray
cd4042bm.step Publish 0.1.0 · Ray
package.json cd4042bm: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
page.json cd4042bm: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md Initial commit: component/cd4042bm · Ray

CD4042BM

lingxingic · Latches · SOP-16

CD4042BM from lingxingic, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q4 output Data output from latch 4.
2 Q1 output Data output from latch 1.
3 Q̄1 output Inverted data output from latch 1.
4 D1 input Data input to latch 1; must be connected to VDD, VSS, or another input if unused.
5 CLOCK input Clock input for all four latches.
6 POLARITY input Clock enable and polarity input; controls latching logic relative to CLOCK.
7 D2 input Data input to latch 2; must be connected to VDD, VSS, or another input if unused.
8 VSS power_in Ground (0V), voltage reference.
9 Q̄2 output Inverted data output from latch 2.
10 Q2 output Data output from latch 2.
11 Q3 output Data output from latch 3.
12 Q̄3 output Inverted data output from latch 3.
13 D3 input Data input to latch 3; must be connected to VDD, VSS, or another input if unused.
14 D4 input Data input to latch 4; must be connected to VDD, VSS, or another input if unused.
15 Q̄4 output Inverted data output from latch 4.
16 VDD power_in Supply voltage, 3V to 15V referenced to VSS.

Key specifications

Parameter Value
Manufacturer lingxingic
Package SOP-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: CD4042BM
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4042bm-etched.step / cd4042bm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4042bm.step / cd4042bm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (15 pp, sha256 e0b95244be641b42, retrieved 2026-09-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF