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CD4040BPWR
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Texas Instruments Counters, Dividers, TSSOP-16. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.
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CD4040BPWR
Texas Instruments · Counters, Dividers · TSSOP-16
CD4040BPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q12 | output | Buffered output of counter stage 12 (the most significant stage). |
| 2 | Q6 | output | Buffered output of counter stage 6. |
| 3 | Q5 | output | Buffered output of counter stage 5. |
| 4 | Q7 | output | Buffered output of counter stage 7. |
| 5 | Q4 | output | Buffered output of counter stage 4. |
| 6 | Q3 | output | Buffered output of counter stage 3. |
| 7 | Q2 | output | Buffered output of counter stage 2. |
| 8 | VSS | power_in | Ground (negative supply) terminal; all voltage ratings are referenced to VSS. |
| 9 | Q1 | output | Buffered output of counter stage 1 (the least significant stage). |
| 10 | φ | input | Input pulse (clock) line with Schmitt-trigger action, so rise and fall times are unlimited; the counter advances one count on each negative transition. |
| 11 | RESET | input | Common reset input; a high level resets the counter to its all-zeros state. |
| 12 | Q9 | output | Buffered output of counter stage 9. |
| 13 | Q8 | output | Buffered output of counter stage 8. |
| 14 | Q10 | output | Buffered output of counter stage 10. |
| 15 | Q11 | output | Buffered output of counter stage 11. |
| 16 | VDD | power_in | Positive supply terminal; recommended 3 V to 18 V over the full temperature range, absolute maximum -0.5 V to +20 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CD4040BPWR - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
cd4040bpwr-etched.step/cd4040bpwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4040bpwr.step/cd4040bpwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (30 pp, sha256
7317dfacb7c3e8db, retrieved 2026-10-20, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CD4040BPWR
**Texas Instruments** · Counters, Dividers · TSSOP-16
CD4040BPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q12 | output | Buffered output of counter stage 12 (the most significant stage). |
| 2 | Q6 | output | Buffered output of counter stage 6. |
| 3 | Q5 | output | Buffered output of counter stage 5. |
| 4 | Q7 | output | Buffered output of counter stage 7. |
| 5 | Q4 | output | Buffered output of counter stage 4. |
| 6 | Q3 | output | Buffered output of counter stage 3. |
| 7 | Q2 | output | Buffered output of counter stage 2. |
| 8 | VSS | power_in | Ground (negative supply) terminal; all voltage ratings are referenced to VSS. |
| 9 | Q1 | output | Buffered output of counter stage 1 (the least significant stage). |
| 10 | φ | input | Input pulse (clock) line with Schmitt-trigger action, so rise and fall times are unlimited; the counter advances one count on each negative transition. |
| 11 | RESET | input | Common reset input; a high level resets the counter to its all-zeros state. |
| 12 | Q9 | output | Buffered output of counter stage 9. |
| 13 | Q8 | output | Buffered output of counter stage 8. |
| 14 | Q10 | output | Buffered output of counter stage 10. |
| 15 | Q11 | output | Buffered output of counter stage 11. |
| 16 | VDD | power_in | Positive supply terminal; recommended 3 V to 18 V over the full temperature range, absolute maximum -0.5 V to +20 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
## CAD (KiCad official)
- Symbol: `CD4040BPWR`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `cd4040bpwr-etched.step` / `cd4040bpwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4040bpwr.step` / `cd4040bpwr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd4040b.pdf) (30 pp, sha256 `7317dfacb7c3e8db`, retrieved 2026-10-20, tier: manufacturer)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cd4040bpwr-datasheet.pdf)