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CD4024BM96

Public Made by Adom

by adom

Texas Instruments Counters, Dividers, SOIC-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs cd4024bm96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers cd4024bm96: viewers · Ray
cd4024bm96-etched.fit.json cd4024bm96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd4024bm96-etched.glb cd4024bm96: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray
cd4024bm96-etched.step cd4024bm96: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray
cd4024bm96.glb Publish 0.1.0 · Ray
cd4024bm96.kicad_mod Publish 0.1.0 · Ray
cd4024bm96.kicad_sym Publish 0.1.0 · Ray
cd4024bm96.lbr Publish 0.1.0 · Ray
cd4024bm96.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json cd4024bm96: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray
README.md cd4024bm96: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray

CD4024BM96

Texas Instruments · Counters, Dividers · SOIC-14

CD4024BM96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 φ input Input pulse (clock). Counter advances one count on the negative (falling) transition of each input pulse. Schmitt-trigger input permits unlimited rise/fall times.
2 RESET input Active-high asynchronous common reset. A high level on RESET clears all seven counter stages (Q1-Q7) to zero.
3 Q7 output Buffered output of the 7th (final) counter stage. Divides the input clock by 128.
4 Q6 output Buffered output of the 6th counter stage. Divides the input clock by 64.
5 Q5 output Buffered output of the 5th counter stage. Divides the input clock by 32.
6 Q4 output Buffered output of the 4th counter stage. Divides the input clock by 16.
7 VSS power_in Negative supply / ground reference. Typically tied to 0 V.
8 NC unconnected No internal connection. Marked NC in the CD4024B terminal-assignment diagram (NC = 8, 10, 13).
9 Q3 output Buffered output of the 3rd counter stage. Divides the input clock by 8.
10 NC unconnected No internal connection. Marked NC in the CD4024B terminal-assignment diagram (NC = 8, 10, 13).
11 Q2 output Buffered output of the 2nd counter stage. Divides the input clock by 4.
12 Q1 output Buffered output of the 1st counter stage. Divides the input clock by 2.
13 NC unconnected No internal connection. Marked NC in the CD4024B terminal-assignment diagram (NC = 8, 10, 13).
14 VDD power_in Positive supply. Rated 3 V to 18 V (absolute max -0.5 V to +20 V). B-series parametrics specified at 5 V, 10 V, and 15 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic
Pins 14

Ordering variants

Same part, different packaging or reel option.

  • CD4024BM96
  • CD4024BM96M
  • CD4024BM96MT
  • CD4024BM96E
  • CD4024BM96F
  • CD4024BM96F3A
  • CD4024BM96NSR
  • CD4024BM96PW
  • CD4024BM96PWR

CAD (KiCad official)

  • Symbol: CD4024BM96
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: cd4024bm96-etched.step / cd4024bm96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4024bm96.step / cd4024bm96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (30 pp, sha256 6c727e4dd1c8af65, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF