component
CD4021BE
Public Made by Adomby adom
Texas Instruments Shift Registers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 23h ago |
| viewers | 23h ago |
| cd4021be-etched.glb | 23h ago |
| cd4021be-etched.step | 23h ago |
| cd4021be-hero.glb | 23h ago |
| cd4021be-hero.overlay.json | 23h ago |
| cd4021be.glb | 23h ago |
| cd4021be.kicad_mod | 23h ago |
| cd4021be.kicad_sym | 23h ago |
| cd4021be.lbr | 23h ago |
| cd4021be.step | 23h ago |
| package.json | 7h ago |
| page.json | 7h ago |
| README.md | 23h ago |
CD4021BE
Texas Instruments · Shift Registers · DIP-16
CD4021BE from Texas Instruments, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PI-8 | input | Parallel jam input to register stage 8, with input voltage limited to -0.5 V to VDD+0.5 V. |
| 2 | Q6 | output | Buffered output from register stage 6. |
| 3 | Q8 | output | Buffered serial output from register stage 8. |
| 4 | PI-4 | input | Parallel jam input to register stage 4, with input voltage limited to -0.5 V to VDD+0.5 V. |
| 5 | PI-3 | input | Parallel jam input to register stage 3, with input voltage limited to -0.5 V to VDD+0.5 V. |
| 6 | PI-2 | input | Parallel jam input to register stage 2, with input voltage limited to -0.5 V to VDD+0.5 V. |
| 7 | PI-1 | input | Parallel jam input to register stage 1, with input voltage limited to -0.5 V to VDD+0.5 V. |
| 8 | VSS | power_in | Ground (negative supply) reference terminal; supply voltages are referenced to VSS. |
| 9 | PARALLEL/SERIAL CONTROL | input | Low shifts data serially on the positive clock edge; high asynchronously jams the parallel inputs into the 8-stage register. |
| 10 | CLOCK | input | Common clock input; serial shifting occurs on the positive clock transition. |
| 11 | SERIAL IN | input | Single serial data input, shifted into the register synchronously with the clock when parallel/serial control is low. |
| 12 | Q7 | output | Buffered output from register stage 7. |
| 13 | PI-5 | input | Parallel jam input to register stage 5, with input voltage limited to -0.5 V to VDD+0.5 V. |
| 14 | PI-6 | input | Parallel jam input to register stage 6, with input voltage limited to -0.5 V to VDD+0.5 V. |
| 15 | PI-7 | input | Parallel jam input to register stage 7, with input voltage limited to -0.5 V to VDD+0.5 V. |
| 16 | VDD | power_in | Positive supply voltage, recommended 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | DIP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CD4021BE - Footprint:
Package_DIP:DIP-16_W7.62mm - 3D model: DIP-16 (KiCad packages3D, STEP)
- 3D model files:
cd4021be-etched.step/cd4021be-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4021be.step/cd4021be.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (29 pp, sha256
078cf8019db65cb7, retrieved 2026-10-06, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).