CD4020S

{
  "slug": "cd4020s",
  "version": "0.1.0",
  "type": "component",
  "description": "GR Counters, Dividers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "cd4020s",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cd4020s.kicad_sym",
    "cd4020s.kicad_mod",
    "cd4020s.glb",
    "cd4020s.step",
    "cd4020s.lbr",
    "docs/hero.png",
    "docs/cd4020s-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "cd4020s-hero.glb",
    "cd4020s-hero.overlay.json",
    "cd4020s-etched.glb"
  ],
  "component": {
    "mpn": "CD4020S",
    "manufacturer": "GR",
    "package": "SOP-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Counters, Dividers",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8597547887995994112",
    "parts": {
      "symbol": "cd4020s.kicad_sym",
      "footprint": "cd4020s.kicad_mod",
      "model_3d": "cd4020s-hero.glb",
      "model_3d_plain": "cd4020s-etched.glb",
      "model_3d_step": "cd4020s-etched.step",
      "model_3d_step_plain": "cd4020s.step",
      "lbr": "cd4020s.lbr"
    },
    "distributor_links": {
      "lcsc": "C19818876"
    },
    "distributor_check": {
      "checked_at": "2026-10-21T02:15:40Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "no match"
      },
      "mouser": {
        "pn": null,
        "status": "no match"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "Q12",
        "type": "output",
        "description": "Binary counter output Q12 from the 14-bit counter chain, using a buffered CMOS output stage."
      },
      {
        "number": "2",
        "name": "Q13",
        "type": "output",
        "description": "Binary counter output Q13 from the 14-bit counter chain, using a buffered CMOS output stage."
      },
      {
        "number": "3",
        "name": "Q14",
        "type": "output",
        "description": "Binary counter output Q14, the most significant stage of the 14-bit counter, using a buffered CMOS output stage."
      },
      {
        "number": "4",
        "name": "Q6",
        "type": "output",
        "description": "Binary counter output Q6 from the 14-bit counter chain, using a buffered CMOS output stage."
      },
      {
        "number": "5",
        "name": "Q5",
        "type": "output",
        "description": "Binary counter output Q5 from the 14-bit counter chain, using a buffered CMOS output stage."
      },
      {
        "number": "6",
        "name": "Q7",
        "type": "output",
        "description": "Binary counter output Q7 from the 14-bit counter chain, using a buffered CMOS output stage."
      },
      {
        "number": "7",
        "name": "Q4",
        "type": "output",
        "description": "Binary counter output Q4 from the 14-bit counter chain, using a buffered CMOS output stage."
      },
      {
        "number": "8",
        "name": "VSS",
        "type": "power_in",
        "description": "Negative supply / ground reference; input voltages are specified relative to VSS."
      },
      {
        "number": "9",
        "name": "Q1",
        "type": "output",
        "description": "Binary counter output Q1, the first counter stage, using a buffered CMOS output stage."
      },
      {
        "number": "10",
        "name": "ф1",
        "type": "input",
        "description": "Clock input CP; the counter advances on the falling edge of CP, and the input uses a Schmitt-trigger circuit. Minimum clock pulse width is 125 ns at VDD=5 V, 50 ns at 10 V and 40 ns at 15 V; maximum clock frequency is 4 MHz at 5 V, 10 MHz at 10 V and 12 MHz at 15 V."
      },
      {
        "number": "11",
        "name": "RESET",
        "type": "input",
        "description": "Output clear (reset) input for the counter; the datasheet intro describes CR as active low, while the timing table gives a minimum reset pulse width tWH(R) of 200 ns at 5 V, 100 ns at 10 V and 80 ns at 15 V."
      },
      {
        "number": "12",
        "name": "Q9",
        "type": "output",
        "description": "Binary counter output Q9 from the 14-bit counter chain, using a buffered CMOS output stage."
      },
      {
        "number": "13",
        "name": "Q8",
        "type": "output",
        "description": "Binary counter output Q8 from the 14-bit counter chain, using a buffered CMOS output stage."
      },
      {
        "number": "14",
        "name": "Q10",
        "type": "output",
        "description": "Binary counter output Q10 from the 14-bit counter chain, using a buffered CMOS output stage."
      },
      {
        "number": "15",
        "name": "Q11",
        "type": "output",
        "description": "Binary counter output Q11 from the 14-bit counter chain, using a buffered CMOS output stage."
      },
      {
        "number": "16",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive supply; recommended operating voltage is 3 V to 15 V and the absolute maximum is -0.5 V to 18 V."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Polarity conflict: the datasheet intro says the clear terminal CR is active low, but the timing tabl; The clock pin is printed as 'ф1' in the pin table and as 'CP' in the text; it is treated here as the; The pinout is a shared DIP16/SOP16 table; the datasheet note says the CDXXXXS suffix denotes SOP16, "
        ],
        "pages_sent": 5,
        "cost_usd": 0.0261,
        "at": "2026-10-21T02:09:41"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8597547887995994112",
        "pages": 5,
        "sha256": "054ac8c7da8c94ee",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "cd4020s.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          9.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
        "checked": "2026-10-21",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cd4020s-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
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        "sha256": "9d6ae61427f111ef3f52d9b4f930b288d9b2c810507ff78e03f96bea8d216f3e",
        "checked": "2026-10-21",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}