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CD4020S

Public Made by Adom

by adom

GR Counters, Dividers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD4020S

GR · Counters, Dividers · SOP-16

CD4020S from GR, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q12 output Binary counter output Q12 from the 14-bit counter chain, using a buffered CMOS output stage.
2 Q13 output Binary counter output Q13 from the 14-bit counter chain, using a buffered CMOS output stage.
3 Q14 output Binary counter output Q14, the most significant stage of the 14-bit counter, using a buffered CMOS output stage.
4 Q6 output Binary counter output Q6 from the 14-bit counter chain, using a buffered CMOS output stage.
5 Q5 output Binary counter output Q5 from the 14-bit counter chain, using a buffered CMOS output stage.
6 Q7 output Binary counter output Q7 from the 14-bit counter chain, using a buffered CMOS output stage.
7 Q4 output Binary counter output Q4 from the 14-bit counter chain, using a buffered CMOS output stage.
8 VSS power_in Negative supply / ground reference; input voltages are specified relative to VSS.
9 Q1 output Binary counter output Q1, the first counter stage, using a buffered CMOS output stage.
10 ф1 input Clock input CP; the counter advances on the falling edge of CP, and the input uses a Schmitt-trigger circuit. Minimum clock pulse width is 125 ns at VDD=5 V, 50 ns at 10 V and 40 ns at 15 V; maximum clock frequency is 4 MHz at 5 V, 10 MHz at 10 V and 12 MHz at 15 V.
11 RESET input Output clear (reset) input for the counter; the datasheet intro describes CR as active low, while the timing table gives a minimum reset pulse width tWH(R) of 200 ns at 5 V, 100 ns at 10 V and 80 ns at 15 V.
12 Q9 output Binary counter output Q9 from the 14-bit counter chain, using a buffered CMOS output stage.
13 Q8 output Binary counter output Q8 from the 14-bit counter chain, using a buffered CMOS output stage.
14 Q10 output Binary counter output Q10 from the 14-bit counter chain, using a buffered CMOS output stage.
15 Q11 output Binary counter output Q11 from the 14-bit counter chain, using a buffered CMOS output stage.
16 VDD power_in Positive supply; recommended operating voltage is 3 V to 15 V and the absolute maximum is -0.5 V to 18 V.

Key specifications

Parameter Value
Manufacturer GR
Package SOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage VIN (absolute max, printed as -0.5+VSS-VDD+0.5V) VIN -0.5 0.5 V Printed as -0.5+VSS-VDD+0.5 V: offsets below VSS (min) and above VDD (max); not absolute volts 2
Supply voltage VDD (absolute max) VDD -0.5 18 V 2
Power dissipation PD PD 500 mW 2
Operating temperature TA (absolute max) TA 0 70 ℃ 2
Storage temperature TS TS -65 150 ℃ 2
Lead soldering temperature TW TW 260 ℃ 10 s 2
Supply voltage VDD (recommended operating) VDD 3 15 V 2
Input/output voltage VIN, Vout (recommended) VIN、Vout 0 V Upper limit printed as VDD 2
Output current IIN, Iout (recommended) IIN、Iout 0 V Upper limit printed as VDD; unit printed as V 2
Operating temperature TA (recommended) TA 0 60 ℃ 2
VIH high-level input voltage VIH 3.5 V TA=25℃, /IO/≤1uA, Vo=0.5V, VDD=5V 3
VIH high-level input voltage VIH 7 V TA=25℃, /IO/≤1uA, Vo=1V, VDD=10V 3
VIH high-level input voltage VIH 11 V TA=25℃, /IO/≤1uA, Vo=1.5V, VDD=15V 3
VIL low-level input voltage VIL 1.5 V TA=25℃, /IO/≤1uA, Vo=4.5V, VDD=5V 3
VIL low-level input voltage VIL 3 V TA=25℃, /IO/≤1uA, Vo=9V, VDD=10V 3
VIL low-level input voltage VIL 4 V TA=25℃, /IO/≤1uA, Vo=13.5V, VDD=15V 3
VOH high-level output voltage VOH 4.95 5 V TA=25℃, /IOUT/<1uA, VDD=5V 3
VOH high-level output voltage VOH 9.95 10 V TA=25℃, /IOUT/<1uA, VDD=10V 3
VOH high-level output voltage VOH 14.95 15 V TA=25℃, /IOUT/<1uA, VDD=15V 3
VOL low-level output voltage VOL 0 0.05 V TA=25℃, /IOUT/<1uA, VDD=5V 3
IIN input current IIN 0.01 1 uA TA=25℃, VIN=VDD or VSS, VDD=15V 3
IOH high-level output current IOH -1 -0.5 mA TA=25℃, Vo=4.6V, VDD=5V 3
IOH high-level output current IOH -2.1 -1.3 mA TA=25℃, Vo=9.5V, VDD=10V 3
IOH high-level output current IOH -8 -3.4 mA TA=25℃, Vo=13.5V, VDD=15V 3
IOL low-level output current IOL 0.5 2.2 mA TA=25℃, Vo=0.4V, VDD=5V 3
IOL low-level output current IOL 1.3 5.1 mA TA=25℃, Vo=0.5V, VDD=10V 3
IOL low-level output current IOL 3.4 19 mA TA=25℃, Vo=1.5V, VDD=15V 3
IDD operating current IDD 0.1 4 uA TA=25℃, VIN=VDD or VSS, VDD=5V 3
IDD operating current IDD 0.1 5 uA TA=25℃, VIN=VDD or VSS, VDD=10V 3
IDD operating current IDD 0.1 6 uA TA=25℃, VIN=VDD or VSS, VDD=15V 3
Transmission delay time ф1, RESET to Q1 tPHL, tPLH 250 ns Ta=25℃, RL=200k, CL=51pF, VDD=5V 4
Transmission delay time ф1, RESET to Q1 tPHL, tPLH 100 ns Ta=25℃, RL=200k, CL=51pF, VDD=10V 4
Transmission delay time ф1, RESET to Q1 tPHL, tPLH 75 ns Ta=25℃, RL=200k, CL=51pF, VDD=15V 4
Adjacent output delay time Qn to Qn+1 tPLH, tPHL 150 ns Ta=25℃, RL=200k, CL=51pF, VDD=5V 4
Adjacent output delay time Qn to Qn+1 tPLH, tPHL 60 ns Ta=25℃, RL=200k, CL=51pF, VDD=10V 4
Adjacent output delay time Qn to Qn+1 tPLH, tPHL 45 ns Ta=25℃, RL=200k, CL=51pF, VDD=15V 4
Output rise/fall time Qn TTLH, TTHL 125 ns Ta=25℃, RL=200k, CL=51pF, VDD=5V 4
Output rise/fall time Qn TTLH, TTHL 50 ns Ta=25℃, RL=200k, CL=51pF, VDD=10V 4
Output rise/fall time Qn TTLH, TTHL 40 ns Ta=25℃, RL=200k, CL=51pF, VDD=15V 4
ф1 clock minimum pulse width TWL, TWH 125 ns Ta=25℃, RL=200k, CL=51pF, VDD=5V 4
ф1 clock minimum pulse width TWL, TWH 50 ns Ta=25℃, RL=200k, CL=51pF, VDD=10V 4
ф1 clock minimum pulse width TWL, TWH 40 ns Ta=25℃, RL=200k, CL=51pF, VDD=15V 4
Clock frequency ф1 Fф1 4 MHz Ta=25℃, RL=200k, CL=51pF, VDD=5V 4
Clock frequency ф1 Fф1 10 MHz Ta=25℃, RL=200k, CL=51pF, VDD=10V 4
Clock frequency ф1 Fф1 12 MHz Ta=25℃, RL=200k, CL=51pF, VDD=15V 4
Reset delay time TPHL(R) 200 ns Ta=25℃, RL=200k, CL=51pF, VDD=5V 4
Reset delay time TPHL(R) 100 ns Ta=25℃, RL=200k, CL=51pF, VDD=10V 4
Reset delay time TPHL(R) 80 ns Ta=25℃, RL=200k, CL=51pF, VDD=15V 4
Reset minimum pulse width tWH(R) 200 ns Ta=25℃, RL=200k, CL=51pF, VDD=5V 4
Reset minimum pulse width tWH(R) 100 ns Ta=25℃, RL=200k, CL=51pF, VDD=10V 4
Reset minimum pulse width tWH(R) 80 ns Ta=25℃, RL=200k, CL=51pF, VDD=15V 4

CAD (KiCad official)

  • Symbol: CD4020S
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4020s-etched.step / cd4020s-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4020s.step / cd4020s.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: GR datasheet (5 pp, sha256 054ac8c7da8c94ee, retrieved 2026-10-21, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF