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docs cd4020: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers interactive viewers · Ray 2mo ago
cd4020-etched.fit.json cd4020: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
cd4020-etched.glb cd4020: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
cd4020-etched.step cd4020: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
cd4020.glb Publish 0.1.0 · Ray 2mo ago
cd4020.kicad_mod Publish 0.1.0 · Ray 2mo ago
cd4020.kicad_sym Publish 0.1.0 · Ray 2mo ago
cd4020.lbr add validated EAGLE .lbr (Fusion library) · Ray 2mo ago
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CD4020B.adom-lbr.json CD4020B: validated Fusion/EAGLE library + adom-lbr hub, generated from this page's KiCad sources · Ray 2mo ago
CD4020B.lbr CD4020B: validated Fusion/EAGLE library + adom-lbr hub, generated from this page's KiCad sources · Ray 2mo ago
package.json Publish 0.1.0 · Ray 2mo ago
page.json cd4020: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 26d ago
README.md cd4020: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago

CD4020B

Texas Instruments · Counter · SOIC-16

The CD4020B is a 14-stage ripple-carry binary counter. Each positive-to-negative clock transition advances the count, and stages Q1 and Q4 through Q14 are available as outputs (Q2 and Q3 are internal). Unlike the CD4060, it takes an external clock rather than having an on-chip oscillator. It runs from 3 V to 18 V.

Pinout

Pin Name Type Function
1 Q12 output Buffered counter output, stage 12 (divide-by-4096).
2 Q13 output Buffered counter output, stage 13 (divide-by-8192).
3 Q14 output Buffered counter output, stage 14 (divide-by-16384).
4 Q6 output Buffered counter output, stage 6 (divide-by-64).
5 Q5 output Buffered counter output, stage 5 (divide-by-32).
6 Q7 output Buffered counter output, stage 7 (divide-by-128).
7 Q4 output Buffered counter output, stage 4 (divide-by-16).
8 VSS power_in Ground reference / negative supply (0 V).
9 Q1 output Buffered counter output, stage 1 (divide-by-2). Stages 2 and 3 are internal and not brought out.
10 CLOCK input Clock input. Counter advances one count on each high-to-low (negative-going) transition. Schmitt-triggered on CD4020B.
11 RESET input Asynchronous master reset, active HIGH. When RESET is high all counter outputs (Q1, Q4-Q14) are forced to logic 0 regardless of the CLOCK state.
12 Q9 output Buffered counter output, stage 9 (divide-by-512).
13 Q8 output Buffered counter output, stage 8 (divide-by-256).
14 Q10 output Buffered counter output, stage 10 (divide-by-1024).
15 Q11 output Buffered counter output, stage 11 (divide-by-2048).
16 VDD power_in Positive supply, 3 V to 18 V (recommended 3 V to 15 V).

Key specifications

Parameter Value
Type 14-stage ripple binary counter
Logic family 4000B (CMOS)
Available outputs Q1, Q4 through Q14 (Q2, Q3 internal)
Clock External, buffered input
Supply voltage 3 V to 18 V
Operating temperature -55 C to 125 C

Ordering variants

Same part, different packaging or reel option.

  • CD4020BE
  • CD4020BEE4
  • CD4020BM
  • CD4020BM96
  • CD4020BMT
  • CD4020BPW
  • CD4020BPWR

CAD (KiCad official)

  • Symbol: cd4020.kicad_sym
  • Footprint: cd4020.kicad_mod
  • 3D model: SOIC-16 body from KiCad Package_SO/SOIC-16_3.9x9.9mm_P1.27mm.
  • 3D model files: cd4020-etched.step / cd4020-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4020.step / cd4020.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (30 pp, sha256 6c727e4dd1c8af65, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF