CD4015BM96

{
  "slug": "cd4015bm96",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "cd4015bm96",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cd4015bm96.kicad_sym",
    "cd4015bm96.kicad_mod",
    "cd4015bm96.glb",
    "cd4015bm96.step",
    "cd4015bm96.lbr",
    "docs/hero.png",
    "docs/cd4015bm96-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "component": {
    "mpn": "CD4015BM96",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Shift Registers",
    "datasheet": "https://www.ti.com/cn/lit/gpn/cd4015b",
    "parts": {
      "symbol": "cd4015bm96.kicad_sym",
      "footprint": "cd4015bm96.kicad_mod",
      "model_3d": "cd4015bm96-etched.glb",
      "model_3d_plain": "cd4015bm96.glb",
      "model_3d_step": "cd4015bm96-etched.step",
      "model_3d_step_plain": "cd4015bm96.step",
      "lbr": "cd4015bm96.lbr"
    },
    "distributor_links": {
      "lcsc": "C2870719"
    },
    "pins": [
      {
        "number": "1",
        "name": "CLOCK B",
        "type": "input",
        "description": "Clock input for register B; the logic level at DATA B is shifted one stage on each positive-going transition of this clock, with rise/fall time and pulse-width limits given in the recommended operating conditions."
      },
      {
        "number": "2",
        "name": "Q4B",
        "type": "output",
        "description": "Parallel output of the fourth (last) stage of shift register B."
      },
      {
        "number": "3",
        "name": "Q3A",
        "type": "output",
        "description": "Parallel output of the third stage of shift register A."
      },
      {
        "number": "4",
        "name": "Q2A",
        "type": "output",
        "description": "Parallel output of the second stage of shift register A."
      },
      {
        "number": "5",
        "name": "Q1A",
        "type": "output",
        "description": "Parallel output of the first stage of shift register A."
      },
      {
        "number": "6",
        "name": "RESET A",
        "type": "input",
        "description": "Reset input for register A; a high level on this pin resets all four stages of register A to logic 0, with minimum reset pulse width specified over VDD."
      },
      {
        "number": "7",
        "name": "DATA A",
        "type": "input",
        "description": "Serial data input for register A; the logic level present is transferred into the first stage and shifted on each positive-going CLOCK A transition, subject to the minimum data setup time."
      },
      {
        "number": "8",
        "name": "VSS",
        "type": "power_in",
        "description": "Negative supply/ground terminal to which all input and supply voltages are referenced (VDD range -0.5V to +20V relative to VSS)."
      },
      {
        "number": "9",
        "name": "CLOCK A",
        "type": "input",
        "description": "Clock input for register A; the logic level at DATA A is shifted one stage on each positive-going transition of this clock, with rise/fall time and pulse-width limits given in the recommended operating conditions."
      },
      {
        "number": "10",
        "name": "Q4A",
        "type": "output",
        "description": "Parallel output of the fourth (last) stage of shift register A."
      },
      {
        "number": "11",
        "name": "Q3B",
        "type": "output",
        "description": "Parallel output of the third stage of shift register B."
      },
      {
        "number": "12",
        "name": "Q2B",
        "type": "output",
        "description": "Parallel output of the second stage of shift register B."
      },
      {
        "number": "13",
        "name": "Q1B",
        "type": "output",
        "description": "Parallel output of the first stage of shift register B."
      },
      {
        "number": "14",
        "name": "RESET B",
        "type": "input",
        "description": "Reset input for register B; a high level on this pin resets all four stages of register B to logic 0, with minimum reset pulse width specified over VDD."
      },
      {
        "number": "15",
        "name": "DATA B",
        "type": "input",
        "description": "Serial data input for register B; the logic level present is transferred into the first stage and shifted on each positive-going CLOCK B transition, subject to the minimum data setup time."
      },
      {
        "number": "16",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive supply pin; DC supply-voltage range is -0.5V to +20V referenced to VSS, with recommended operation from 3V to 18V."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.2",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.2",
        "primary_model": "claude-sonnet-5",
        "primary_mode": "text+vision",
        "consensus_model": "claude-opus-4-8",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "vision extraction: provenance cannot be text-verified; needs consensus"
        ],
        "pages_sent": 16,
        "cost_usd": 0.5921,
        "at": "2026-09-24T03:28:53"
      },
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/cd4015b",
        "pages": 16,
        "sha256": "1737b3cedb44d5c1",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "cd4015bm96.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          9.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cd4015bm96-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
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        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "d207bae58d0751891452db99e413b825cc111545baa9e40e93196c3a624fb8a7",
        "checked": "2026-10-19",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}