component
CD4015BM96
Public Made by Adomby adom
Texas Instruments Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
CD4015BM96
Texas Instruments · Shift Registers · SOIC-16
CD4015BM96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLOCK B | input | Clock input for register B; the logic level at DATA B is shifted one stage on each positive-going transition of this clock, with rise/fall time and pulse-width limits given in the recommended operating conditions. |
| 2 | Q4B | output | Parallel output of the fourth (last) stage of shift register B. |
| 3 | Q3A | output | Parallel output of the third stage of shift register A. |
| 4 | Q2A | output | Parallel output of the second stage of shift register A. |
| 5 | Q1A | output | Parallel output of the first stage of shift register A. |
| 6 | RESET A | input | Reset input for register A; a high level on this pin resets all four stages of register A to logic 0, with minimum reset pulse width specified over VDD. |
| 7 | DATA A | input | Serial data input for register A; the logic level present is transferred into the first stage and shifted on each positive-going CLOCK A transition, subject to the minimum data setup time. |
| 8 | VSS | power_in | Negative supply/ground terminal to which all input and supply voltages are referenced (VDD range -0.5V to +20V relative to VSS). |
| 9 | CLOCK A | input | Clock input for register A; the logic level at DATA A is shifted one stage on each positive-going transition of this clock, with rise/fall time and pulse-width limits given in the recommended operating conditions. |
| 10 | Q4A | output | Parallel output of the fourth (last) stage of shift register A. |
| 11 | Q3B | output | Parallel output of the third stage of shift register B. |
| 12 | Q2B | output | Parallel output of the second stage of shift register B. |
| 13 | Q1B | output | Parallel output of the first stage of shift register B. |
| 14 | RESET B | input | Reset input for register B; a high level on this pin resets all four stages of register B to logic 0, with minimum reset pulse width specified over VDD. |
| 15 | DATA B | input | Serial data input for register B; the logic level present is transferred into the first stage and shifted on each positive-going CLOCK B transition, subject to the minimum data setup time. |
| 16 | VDD | power_in | Positive supply pin; DC supply-voltage range is -0.5V to +20V referenced to VSS, with recommended operation from 3V to 18V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CD4015BM96 - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
cd4015bm96-etched.step/cd4015bm96-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4015bm96.step/cd4015bm96.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (16 pp, sha256
1737b3cedb44d5c1, retrieved 2026-09-24, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-sonnet-5(text+vision), consensusclaude-opus-4-8(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).