CD4012NS14ARDQ

{
  "slug": "cd4012ns14ardq",
  "version": "0.1.0",
  "type": "component",
  "description": "GR Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "cd4012ns14ardq",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cd4012ns14ardq.kicad_sym",
    "cd4012ns14ardq.kicad_mod",
    "cd4012ns14ardq.glb",
    "cd4012ns14ardq.step",
    "cd4012ns14ardq.lbr",
    "docs/hero.png",
    "docs/cd4012ns14ardq-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "cd4012ns14ardq-hero.glb",
    "cd4012ns14ardq-hero.overlay.json",
    "cd4012ns14ardq-etched.glb"
  ],
  "component": {
    "mpn": "CD4012NS14ARDQ",
    "manufacturer": "GR",
    "package": "SOP-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Logic Gates",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603388397201473536",
    "parts": {
      "symbol": "cd4012ns14ardq.kicad_sym",
      "footprint": "cd4012ns14ardq.kicad_mod",
      "model_3d": "cd4012ns14ardq-hero.glb",
      "model_3d_plain": "cd4012ns14ardq-etched.glb",
      "model_3d_step": "cd4012ns14ardq-etched.step",
      "model_3d_step_plain": "cd4012ns14ardq.step",
      "lbr": "cd4012ns14ardq.lbr"
    },
    "distributor_links": {
      "lcsc": "C27975226"
    },
    "distributor_check": {
      "checked_at": "2026-10-17T06:06:02Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "no match"
      },
      "mouser": {
        "pn": null,
        "status": "no match"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "1Y",
        "type": "output",
        "description": "Data output of NAND gate 1, the NAND of inputs 1A to 1D."
      },
      {
        "number": "2",
        "name": "1A",
        "type": "input",
        "description": "Data input A of NAND gate 1, buffered input."
      },
      {
        "number": "3",
        "name": "1B",
        "type": "input",
        "description": "Data input B of NAND gate 1, buffered input."
      },
      {
        "number": "4",
        "name": "1C",
        "type": "input",
        "description": "Data input C of NAND gate 1, buffered input."
      },
      {
        "number": "5",
        "name": "1D",
        "type": "input",
        "description": "Data input D of NAND gate 1, buffered input."
      },
      {
        "number": "6",
        "name": "NC",
        "type": "unconnected",
        "description": "Not connected."
      },
      {
        "number": "7",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground reference; all voltages are referenced to VSS."
      },
      {
        "number": "8",
        "name": "NC",
        "type": "unconnected",
        "description": "Not connected."
      },
      {
        "number": "9",
        "name": "2A",
        "type": "input",
        "description": "Data input A of NAND gate 2, buffered input."
      },
      {
        "number": "10",
        "name": "2B",
        "type": "input",
        "description": "Data input B of NAND gate 2, buffered input."
      },
      {
        "number": "11",
        "name": "2C",
        "type": "input",
        "description": "Data input C of NAND gate 2, buffered input."
      },
      {
        "number": "12",
        "name": "2D",
        "type": "input",
        "description": "Data input D of NAND gate 2, buffered input."
      },
      {
        "number": "13",
        "name": "2Y",
        "type": "output",
        "description": "Data output of NAND gate 2, the NAND of inputs 2A to 2D."
      },
      {
        "number": "14",
        "name": "VDD",
        "type": "power_in",
        "description": "Supply voltage; absolute maximum DC supply is 20 V with respect to VSS (rated range -0.5 V to 20 V)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The datasheet has one pin table (page 2) that is not labelled per package. It is assumed to apply to; The VDD description combines the pin table with the absolute maximum rating from page 3. The datashe; Pins 6 and 8 are marked NC in the datasheet; they are reported as unconnected and should not be wire"
        ],
        "pages_sent": 7,
        "cost_usd": 0.0285,
        "at": "2026-10-17T06:05:40"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603388397201473536",
        "pages": 7,
        "sha256": "c634f97d9af272f8",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "cd4012ns14ardq.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          8.7,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",
        "checked": "2026-10-17",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cd4012ns14ardq-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          8.7,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "8d561170d1ef30fc5a711d9f4ac0366257bd6ff2256786fb5b82483325a77308",
        "checked": "2026-10-17",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}