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Generated by kicad-footprint-generator · KiCad file format 20260206

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cd4012ns14ardq-etched.step	cd4012ns14ardq: factory component page (tier=lcsc) · Ray	6d ago
cd4012ns14ardq-hero.glb	cd4012ns14ardq: hero GLB from the etched model (keeps the MPN mark) · Ray	6d ago
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CD4012NS14ARDQ

GR · Logic Gates · SOP-14

CD4012NS14ARDQ from GR, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	1Y	output	Data output of NAND gate 1, the NAND of inputs 1A to 1D.
2	1A	input	Data input A of NAND gate 1, buffered input.
3	1B	input	Data input B of NAND gate 1, buffered input.
4	1C	input	Data input C of NAND gate 1, buffered input.
5	1D	input	Data input D of NAND gate 1, buffered input.
6	NC	unconnected	Not connected.
7	VSS	power_in	Ground reference; all voltages are referenced to VSS.
8	NC	unconnected	Not connected.
9	2A	input	Data input A of NAND gate 2, buffered input.
10	2B	input	Data input B of NAND gate 2, buffered input.
11	2C	input	Data input C of NAND gate 2, buffered input.
12	2D	input	Data input D of NAND gate 2, buffered input.
13	2Y	output	Data output of NAND gate 2, the NAND of inputs 2A to 2D.
14	VDD	power_in	Supply voltage; absolute maximum DC supply is 20 V with respect to VSS (rated range -0.5 V to 20 V).

Key specifications

Parameter	Value
Manufacturer	GR
Package	SOP-14
Category	Logic
Pins	14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
DC Supply Voltage Range (referenced to VSS)	VDD	-0.5		20	V	Voltage referenced to VSS terminals	3
Input Voltage Range, All Inputs	VI	0.5			V		3
Power Dissipation	PD			500	mW		3
Junction Temperature	TJ			125	℃		3
Operating Temperature	TOP	-40		85	℃		3
Supply Current	IDD		0	1	uA	VIN=0,5 V; VDD=5 V	3
Low Level Output Current	IOL	1.5	3		mA	VO=0.4 V; VIN=0,5 V; VDD=5 V	3
Low Level Output Current	IOL	4	8		mA	VO=0.5 V; VIN=0,10 V; VDD=10 V	3
Low Level Output Current	IOL	15	30		mA	VO=1.5 V; VIN=0,15 V; VDD=15 V	3
High Level Output Current	IOH	-0.5	-2		mA	VO=4.6 V; VIN=0,5 V; VDD=5 V	3
High Level Output Current	IOH	-4	-8		mA	VO=2.5 V; VIN=0,5 V; VDD=5 V	3
High Level Output Current	IOH	-2	-4		mA	VO=9.5 V; VIN=0,10 V; VDD=10 V	3
High Level Output Current	IOH	-7	-14		mA	VO=13.5 V; VIN=0,15 V; VDD=15 V	3
Low Level Output Voltage	VOL		0	0.05	V	VIN=0,5 V; VDD=5 V	3
High Level Output Voltage	VOH	4.95	5		V	VIN=0,5 V; VDD=5 V	3
High Level Output Voltage	VOH	9.95	10		V	VIN=0,10 V; VDD=10 V	3
High Level Output Voltage	VOH	14.95	15		V	VIN=0,15 V; VDD=15 V	3
Low Level Input Voltage	VIL			1.5	V	VO=0.5,4.5 V; VDD=5 V	3
Low Level Input Voltage	VIL			3	V	VO=1,9 V; VDD=10 V	3
Low Level Input Voltage	VIL			4	V	VO=1.5,13.5 V; VDD=15 V	3
High Level Input Voltage	VIH	3.5			V	VO=0.5,4.5 V; VDD=5 V	3
High Level Input Voltage	VIH	7			V	VO=1,9 V; VDD=10 V	3
High Level Input Voltage	VIH	11			V	VO=1.5,13.5 V; VDD=15 V	3
Input Leakage Current	IIN	-1	0	1	uA	VIN=0,18 V; VDD=18 V	3

CAD (KiCad official)

Symbol: CD4012NS14ARDQ
Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
3D model: SOP-14 (KiCad packages3D, STEP)
3D model files: cd4012ns14ardq-etched.step / cd4012ns14ardq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4012ns14ardq.step / cd4012ns14ardq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: GR datasheet (7 pp, sha256 c634f97d9af272f8, retrieved 2026-10-17, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF