component
CD4012BM
Public Made by Adomby adom
lingxingic Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"title": "CD4012BM",
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"package": "SOP-14",
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"category": "Logic",
"subcategory": "Logic Gates",
"datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603345039142121472",
"parts": {
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"footprint": "cd4012bm.kicad_mod",
"model_3d": "cd4012bm-hero.glb",
"model_3d_plain": "cd4012bm-etched.glb",
"model_3d_step": "cd4012bm-etched.step",
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"checked_at": "2026-10-18T13:31:35Z",
"source": "Component Ocean /api/assign-pns",
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"name": "1Y",
"type": "output",
"description": "Output of NAND gate 1; fully buffered, and it goes LOW only when all four of 1A, 1B, 1C and 1D are HIGH."
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{
"number": "2",
"name": "1A",
"type": "input",
"description": "Data input 1A of NAND gate 1; unused inputs must be connected to VDD, GND, or another input."
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{
"number": "3",
"name": "1B",
"type": "input",
"description": "Data input 1B of NAND gate 1; unused inputs must be connected to VDD, GND, or another input."
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{
"number": "4",
"name": "1C",
"type": "input",
"description": "Data input 1C of NAND gate 1; unused inputs must be connected to VDD, GND, or another input."
},
{
"number": "5",
"name": "1D",
"type": "input",
"description": "Data input 1D of NAND gate 1; unused inputs must be connected to VDD, GND, or another input."
},
{
"number": "6",
"name": "NC",
"type": "unconnected",
"description": "No connection."
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{
"number": "7",
"name": "GND",
"type": "power_in",
"description": "Ground reference (0 V); all voltages are referenced to GND, and VDD must be within 3 V to 15 V recommended operating range."
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{
"number": "8",
"name": "NC",
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"description": "No connection."
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{
"number": "9",
"name": "2A",
"type": "input",
"description": "Data input 2A of NAND gate 2; unused inputs must be connected to VDD, GND, or another input."
},
{
"number": "10",
"name": "2B",
"type": "input",
"description": "Data input 2B of NAND gate 2; unused inputs must be connected to VDD, GND, or another input."
},
{
"number": "11",
"name": "2C",
"type": "input",
"description": "Data input 2C of NAND gate 2; unused inputs must be connected to VDD, GND, or another input."
},
{
"number": "12",
"name": "2D",
"type": "input",
"description": "Data input 2D of NAND gate 2; unused inputs must be connected to VDD, GND, or another input."
},
{
"number": "13",
"name": "2Y",
"type": "output",
"description": "Output of NAND gate 2; fully buffered, and it goes LOW only when all four of 2A, 2B, 2C and 2D are HIGH."
},
{
"number": "14",
"name": "VDD",
"type": "power_in",
"description": "Supply voltage, recommended range 3 V to 15 V referenced to GND; absolute maximum is 18 V."
}
],
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"extractor": "extract_pins 0.3",
"factory_chain": {
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"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The ordering table lists CD4012BM, CD4012BPWR and CD4012BE without clearly tying each part number to; The pin configuration figure text is garbled in extraction. Pin numbers and names were taken from th; The datasheet lists no pin-level electrical limits beyond the supply voltage and the ±10 mA DC input"
],
"pages_sent": 14,
"cost_usd": 0.052,
"at": "2026-10-18T13:29:12"
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"sha256": "eb56392bc477561c",
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"cad": "KiCad official (CC-BY-SA 4.0)",
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"described": 14,
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{
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"Package": "SOP-14",
"Category": "Logic",
"Pins": "14"
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{
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{
"name": "total power dissipation",
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"name": "soldering temperature",
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"name": "LOW-level output current",
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{
"name": "LOW-level output current",
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"name": "HIGH-level output current",
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"name": "HIGH-level output current",
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"name": "HIGH-level input voltage",
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"name": "input leakage current",
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"name": "HIGH-level output current",
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