Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

CD4012BM

lingxingic · Logic Gates · SOP-14

CD4012BM from lingxingic, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1Y output Output of NAND gate 1; fully buffered, and it goes LOW only when all four of 1A, 1B, 1C and 1D are HIGH.
2 1A input Data input 1A of NAND gate 1; unused inputs must be connected to VDD, GND, or another input.
3 1B input Data input 1B of NAND gate 1; unused inputs must be connected to VDD, GND, or another input.
4 1C input Data input 1C of NAND gate 1; unused inputs must be connected to VDD, GND, or another input.
5 1D input Data input 1D of NAND gate 1; unused inputs must be connected to VDD, GND, or another input.
6 NC unconnected No connection.
7 GND power_in Ground reference (0 V); all voltages are referenced to GND, and VDD must be within 3 V to 15 V recommended operating range.
8 NC unconnected No connection.
9 2A input Data input 2A of NAND gate 2; unused inputs must be connected to VDD, GND, or another input.
10 2B input Data input 2B of NAND gate 2; unused inputs must be connected to VDD, GND, or another input.
11 2C input Data input 2C of NAND gate 2; unused inputs must be connected to VDD, GND, or another input.
12 2D input Data input 2D of NAND gate 2; unused inputs must be connected to VDD, GND, or another input.
13 2Y output Output of NAND gate 2; fully buffered, and it goes LOW only when all four of 2A, 2B, 2C and 2D are HIGH.
14 VDD power_in Supply voltage, recommended range 3 V to 15 V referenced to GND; absolute maximum is 18 V.

Key specifications

Parameter Value
Manufacturer lingxingic
Package SOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VDD 3 15 V 7
ambient temperature Tamb -40 125 ℃ in free air 7
supply voltage VDD -0.5 18 V 7
DC input current IIK -10 10 mA any one input 7
input voltage VI -0.5 V 7
storage temperature Tstg -65 150 ℃ 7
total power dissipation Ptot 500 mW 7
device dissipation per output transistor P 100 mW per output transistor 7
soldering temperature TL 260 ℃ 10s, SOP/TSSOP 7
supply current IDD 1 uA VIN=0,5; VDD=5V; Tamb=25℃ 7
LOW-level output current IOL 0.51 1 mA VO=0.4; VIN=0,5; VDD=5V; Tamb=25℃ 7
LOW-level output current IOL 1.3 2.6 mA VO=0.5; VIN=0,10; VDD=10V; Tamb=25℃ 7
LOW-level output current IOL 3.4 6.8 mA VO=1.5; VIN=0,15; VDD=15V; Tamb=25℃ 7
HIGH-level output current IOH -0.51 -1 mA VO=4.6; VIN=0,5; VDD=5V; Tamb=25℃ 7
HIGH-level output current IOH -1.6 -3.2 mA VO=2.5; VIN=0,5; VDD=5V; Tamb=25℃ 7
HIGH-level output current IOH -1.3 -2.6 mA VO=9.5; VIN=0,10; VDD=10V; Tamb=25℃ 7
HIGH-level output current IOH -3.4 -6.8 mA VO=13.5; VIN=0,15; VDD=15V; Tamb=25℃ 7
LOW-level output voltage VOL 0 0.05 V VIN=0,5; VDD=5V; Tamb=25℃ 7
HIGH-level output voltage VOH 4.95 5 V VIN=0,5; VDD=5V; Tamb=25℃ 7
HIGH-level output voltage VOH 9.95 10 V VIN=0,10; VDD=10V; Tamb=25℃ 7
HIGH-level output voltage VOH 14.95 15 V VIN=0,15; VDD=15V; Tamb=25℃ 7
LOW-level input voltage VIL 1.5 V VO=4.5; VDD=5V; Tamb=25℃ 7
LOW-level input voltage VIL 3 V VO=9; VDD=10V; Tamb=25℃ 7
LOW-level input voltage VIL 4 V VO=13.5; VDD=15V; Tamb=25℃ 7
HIGH-level input voltage VIH 3.5 V VO=0.5, 4.5 as printed; VDD=5V; Tamb=25℃ 7
HIGH-level input voltage VIH 7 V VO=1, 9 as printed; VDD=10V; Tamb=25℃ 8
HIGH-level input voltage VIH 11 V VO=1.5, 13.5 as printed; VDD=15V; Tamb=25℃ 8
input leakage current II -1 1 uA VIN=0,15; VDD=15V; Tamb=25℃ 8
supply current IDD 1 uA Tamb=-40℃; VIN=0,5; VDD=5V 8
supply current IDD 7.5 uA Tamb=+125℃; VIN=0,5; VDD=5V 8
supply current IDD 15 uA Tamb=+125℃; VIN=0,10; VDD=10V 8
supply current IDD 30 uA Tamb=+125℃; VIN=0,15; VDD=15V 8
LOW-level output current IOL 0.61 mA Tamb=-40℃; VO=0.4; VIN=0,5; VDD=5V 8
LOW-level output current IOL 1.5 mA Tamb=-40℃; VO=0.5; VIN=0,10; VDD=10V 8
LOW-level output current IOL 4 mA Tamb=-40℃; VO=1.5; VIN=0,15; VDD=15V 8
LOW-level output current IOL 0.36 mA Tamb=+125℃; VO=0.4; VIN=0,5; VDD=5V 8
LOW-level output current IOL 0.9 mA Tamb=+125℃; VO=0.5; VIN=0,10; VDD=10V 8
LOW-level output current IOL 2.4 mA Tamb=+125℃; VO=1.5; VIN=0,15; VDD=15V 8
HIGH-level output current IOH -0.61 mA Tamb=-40℃; VO=4.6; VIN=0,5; VDD=5V 8
HIGH-level output current IOH -1.8 mA Tamb=-40℃; VO=2.5; VIN=0,5; VDD=5V 8
HIGH-level output current IOH -1.5 mA Tamb=-40℃; VO=9.5; VIN=0,10; VDD=10V 8
HIGH-level output current IOH -4 mA Tamb=-40℃; VO=13.5; VIN=0,15; VDD=15V 8
HIGH-level output current IOH -0.36 mA Tamb=+125℃; VO=4.6; VIN=0,5; VDD=5V 8
HIGH-level output current IOH -1.15 mA Tamb=+125℃; VO=2.5; VIN=0,5; VDD=5V 8
HIGH-level output current IOH -0.9 mA Tamb=+125℃; VO=9.5; VIN=0,10; VDD=10V 8
HIGH-level output current IOH -2.4 mA Tamb=+125℃; VO=13.5; VIN=0,15; VDD=15V 8
propagation delay time tPHL, tPLH tPHL, tPLH 125 250 ns see Figure 5; VDD=5V; Tamb=25℃ 9
propagation delay time tPHL, tPLH tPHL, tPLH 60 120 ns see Figure 5; VDD=10V; Tamb=25℃ 9
propagation delay time tPHL, tPLH tPHL, tPLH 45 90 ns see Figure 5; VDD=15V; Tamb=25℃ 9
transition time tTHL, tTLH tTHL, tTLH 100 200 ns see Figure 5; VDD=5V; Tamb=25℃ 9
transition time tTHL, tTLH tTHL, tTLH 50 100 ns see Figure 5; VDD=10V; Tamb=25℃ 9
transition time tTHL, tTLH tTHL, tTLH 40 80 ns see Figure 5; VDD=15V; Tamb=25℃ 9
input capacitance CI 5 7.5 pF any input; Tamb=25℃ 9

CAD (KiCad official)

  • Symbol: CD4012BM
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4012bm-etched.step / cd4012bm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4012bm.step / cd4012bm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (14 pp, sha256 eb56392bc477561c, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF