main
Ray cd4011ubmt: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) 5a0a3ed
{
  "schema_version": 1,
  "type": "component",
  "slug": "cd4011ubmt",
  "title": "CD4011UBMT",
  "brief": "Texas Instruments Logic Gates, SOIC-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "cd4011ubmt"
  ],
  "component": {
    "mpn": "CD4011UBMT",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Logic Gates",
    "datasheet": "https://www.ti.com/cn/lit/gpn/cd4011ub",
    "parts": {
      "symbol": "cd4011ubmt.kicad_sym",
      "footprint": "cd4011ubmt.kicad_mod",
      "model_3d": "cd4011ubmt-etched.glb",
      "model_3d_plain": "cd4011ubmt.glb",
      "model_3d_step": "cd4011ubmt-etched.step",
      "model_3d_step_plain": "cd4011ubmt.step",
      "lbr": "cd4011ubmt.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "1A",
        "type": "input",
        "description": "Gate 1 input A. High-impedance CMOS logic input for the first 2-input NAND gate; VIH/VIL scale with VDD (typ. VDD=5 V: VIH>=3.5 V, VIL<=1.5 V). Unused inputs must be tied to VDD or VSS."
      },
      {
        "number": "2",
        "name": "1B",
        "type": "input",
        "description": "Gate 1 input B. High-impedance CMOS logic input for the first 2-input NAND gate. Combined with 1A per Y = NAND(1A,1B). Unused inputs must be tied to VDD or VSS."
      },
      {
        "number": "3",
        "name": "1Y",
        "type": "output",
        "description": "Gate 1 output. Unbuffered CMOS push-pull output; Y = NOT(1A AND 1B). Typical sink/source ~1 mA at VDD=5 V."
      },
      {
        "number": "4",
        "name": "2Y",
        "type": "output",
        "description": "Gate 2 output. Unbuffered CMOS push-pull output; Y = NOT(2A AND 2B)."
      },
      {
        "number": "5",
        "name": "2A",
        "type": "input",
        "description": "Gate 2 input A. High-impedance CMOS logic input for the second 2-input NAND gate."
      },
      {
        "number": "6",
        "name": "2B",
        "type": "input",
        "description": "Gate 2 input B. High-impedance CMOS logic input for the second 2-input NAND gate."
      },
      {
        "number": "7",
        "name": "VSS",
        "type": "power_in",
        "description": "Negative supply / ground reference for all four gates. Typically 0 V. Decoupling of VDD to VSS with 0.1 uF close to the device is recommended."
      },
      {
        "number": "8",
        "name": "3B",
        "type": "input",
        "description": "Gate 3 input B. High-impedance CMOS logic input for the third 2-input NAND gate."
      },
      {
        "number": "9",
        "name": "3A",
        "type": "input",
        "description": "Gate 3 input A. High-impedance CMOS logic input for the third 2-input NAND gate."
      },
      {
        "number": "10",
        "name": "3Y",
        "type": "output",
        "description": "Gate 3 output. Unbuffered CMOS push-pull output; Y = NOT(3A AND 3B)."
      },
      {
        "number": "11",
        "name": "4Y",
        "type": "output",
        "description": "Gate 4 output. Unbuffered CMOS push-pull output; Y = NOT(4A AND 4B)."
      },
      {
        "number": "12",
        "name": "4B",
        "type": "input",
        "description": "Gate 4 input B. High-impedance CMOS logic input for the fourth 2-input NAND gate."
      },
      {
        "number": "13",
        "name": "4A",
        "type": "input",
        "description": "Gate 4 input A. High-impedance CMOS logic input for the fourth 2-input NAND gate."
      },
      {
        "number": "14",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive supply for all four gates. Operating range 3 V to 18 V (CD4000B family). Decouple to VSS with 0.1 uF placed close to the device."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/cd4011ub",
        "pages": null,
        "sha256": "bedb07024c5e0703",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "logic": {
      "family_id": "CD4011",
      "logic_family": "CD4000",
      "function_code": "4011",
      "function_class": "Gate",
      "function_name": "Quad 2-Input NAND Gate",
      "manufacturer": "Texas Instruments",
      "is_specialty": false
    },
    "models_3d": [
      {
        "file": "cd4011ubmt.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          8.7,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cd4011ubmt-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          8.7,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "d77337229a318cb73672a7d89008d636d0e2486b82f688bf60c83bf01c835bdf",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Texas Instruments",
      "Package": "SOIC-14",
      "Category": "Logic",
      "Pins": "14"
    }
  },
  "variants": [
    {
      "mpn": "CD4011UBMT",
      "kind": "packaging"
    },
    {
      "mpn": "CD4011UBMTM",
      "kind": "packaging"
    },
    {
      "mpn": "CD4011UBMTM96",
      "kind": "packaging"
    },
    {
      "mpn": "CD4011UBMTMR",
      "kind": "packaging"
    },
    {
      "mpn": "CD4011UBMTE",
      "kind": "packaging"
    },
    {
      "mpn": "CD4011UBMTEE4",
      "kind": "packaging"
    },
    {
      "mpn": "CD4011UBMTF",
      "kind": "packaging"
    },
    {
      "mpn": "CD4011UBMTF3A",
      "kind": "packaging"
    },
    {
      "mpn": "CD4011UBMTNSR",
      "kind": "packaging"
    },
    {
      "mpn": "CD4011UBMTPW",
      "kind": "packaging"
    },
    {
      "mpn": "CD4011UBMTPWR",
      "kind": "packaging"
    }
  ],
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "cd4011ubmt"
  ],
  "discovery_pitch": "CD4011UBMT (Texas Instruments) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cd4011ubmt.kicad_sym",
    "cd4011ubmt.kicad_mod",
    "cd4011ubmt.glb",
    "cd4011ubmt.step",
    "cd4011ubmt.lbr",
    "docs/hero.png",
    "docs/cd4011ubmt-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "updated_at": "2026-09-24T18:38:37.643Z"
}