CD4011BPWR

{
  "schema_version": 1,
  "type": "component",
  "slug": "cd4011bpwr",
  "title": "CD4011BPWR",
  "brief": "Texas Instruments Gates, TSSOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.2.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "cd4011bpwr"
  ],
  "component": {
    "mpn": "CD4011BPWR",
    "manufacturer": "Texas Instruments",
    "package": "TSSOP-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Gates",
    "datasheet": "https://www.ti.com/lit/ds/symlink/cd4011b.pdf",
    "parts": {
      "symbol": "cd4011bpwr.kicad_sym",
      "footprint": "cd4011bpwr.kicad_mod",
      "model_3d": "cd4011bpwr-etched.glb",
      "model_3d_plain": "cd4011bpwr.glb",
      "model_3d_step": "cd4011bpwr-etched.step",
      "model_3d_step_plain": "cd4011bpwr.step",
      "lbr": "cd4011bpwr.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "1A",
        "type": "input",
        "description": "Gate 1 input A. CMOS logic input, VIH = 3.5 V min at VDD = 5 V. Protected by internal CMOS clamp network to VDD and VSS."
      },
      {
        "number": "2",
        "name": "1B",
        "type": "input",
        "description": "Gate 1 input B. CMOS logic input, VIH = 3.5 V min at VDD = 5 V. Protected by internal CMOS clamp network to VDD and VSS."
      },
      {
        "number": "3",
        "name": "1Y",
        "type": "output",
        "description": "Gate 1 output, Y = NAND(1A, 1B). Buffered CMOS output; IOL/IOH typ 1 mA at VDD = 5 V."
      },
      {
        "number": "4",
        "name": "2Y",
        "type": "output",
        "description": "Gate 2 output, Y = NAND(2A, 2B). Buffered CMOS output; IOL/IOH typ 1 mA at VDD = 5 V."
      },
      {
        "number": "5",
        "name": "2A",
        "type": "input",
        "description": "Gate 2 input A. CMOS logic input, VIH = 3.5 V min at VDD = 5 V."
      },
      {
        "number": "6",
        "name": "2B",
        "type": "input",
        "description": "Gate 2 input B. CMOS logic input, VIH = 3.5 V min at VDD = 5 V."
      },
      {
        "number": "7",
        "name": "VSS",
        "type": "power_in",
        "description": "Negative supply / ground reference. Normally tied to 0 V. All input and output voltages are referenced to this pin."
      },
      {
        "number": "8",
        "name": "3A",
        "type": "input",
        "description": "Gate 3 input A. CMOS logic input, VIH = 3.5 V min at VDD = 5 V."
      },
      {
        "number": "9",
        "name": "3B",
        "type": "input",
        "description": "Gate 3 input B. CMOS logic input, VIH = 3.5 V min at VDD = 5 V."
      },
      {
        "number": "10",
        "name": "3Y",
        "type": "output",
        "description": "Gate 3 output, Y = NAND(3A, 3B). Buffered CMOS output; IOL/IOH typ 1 mA at VDD = 5 V."
      },
      {
        "number": "11",
        "name": "4Y",
        "type": "output",
        "description": "Gate 4 output, Y = NAND(4A, 4B). Buffered CMOS output; IOL/IOH typ 1 mA at VDD = 5 V."
      },
      {
        "number": "12",
        "name": "4A",
        "type": "input",
        "description": "Gate 4 input A. CMOS logic input, VIH = 3.5 V min at VDD = 5 V."
      },
      {
        "number": "13",
        "name": "4B",
        "type": "input",
        "description": "Gate 4 input B. CMOS logic input, VIH = 3.5 V min at VDD = 5 V."
      },
      {
        "number": "14",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive supply. Recommended operating range 3 V to 18 V (absolute maximum -0.5 V to +20 V referenced to VSS). Bypass to VSS with a local decoupling capacitor."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/cd4011b.pdf",
        "pages": 23,
        "sha256": "92d82fa35555e4e4",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "logic": {
      "family_id": "CD4011",
      "logic_family": "CD4000",
      "function_code": "4011",
      "function_class": "Gate",
      "function_name": "Quad 2-Input NAND Gate",
      "manufacturer": "Texas Instruments",
      "is_specialty": false
    },
    "models_3d": [
      {
        "file": "cd4011bpwr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          5.0,
          1.0
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3ee5786aae56190997aa793ba3cfc003fd616782770e29719b4562f012982245",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cd4011bpwr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          5.0,
          1.0
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "f0098b379da9834e194b89fc15afa50ca66a1ae4d333454a55c601bceff789c4",
        "checked": "2026-10-19",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Texas Instruments",
      "Package": "TSSOP-14",
      "Category": "Logic",
      "Pins": "14"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "cd4011bpwr"
  ],
  "discovery_pitch": "CD4011BPWR (Texas Instruments) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cd4011bpwr.kicad_sym",
    "cd4011bpwr.kicad_mod",
    "cd4011bpwr.glb",
    "cd4011bpwr.step",
    "cd4011bpwr-etched.step",
    "cd4011bpwr.lbr",
    "docs/hero.png",
    "docs/cd4011bpwr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "variants": [
    {
      "mpn": "CD4011BPWR",
      "kind": "packaging"
    },
    {
      "mpn": "CD4011BPWRG4",
      "kind": "packaging"
    },
    {
      "mpn": "CD4011BPWRE",
      "kind": "packaging"
    },
    {
      "mpn": "CD4011BPWREE4",
      "kind": "packaging"
    },
    {
      "mpn": "CD4011BPWRF",
      "kind": "packaging"
    },
    {
      "mpn": "CD4011BPWRF3A",
      "kind": "packaging"
    },
    {
      "mpn": "CD4011BPWRM",
      "kind": "packaging"
    },
    {
      "mpn": "CD4011BPWRM96",
      "kind": "packaging"
    },
    {
      "mpn": "CD4011BPWRME4",
      "kind": "packaging"
    },
    {
      "mpn": "CD4011BPWRM96E4",
      "kind": "packaging"
    },
    {
      "mpn": "CD4011BPWRMT",
      "kind": "packaging"
    },
    {
      "mpn": "CD4011BPWRNSR",
      "kind": "packaging"
    }
  ],
  "updated_at": "2026-09-24T18:38:21.989Z"
}