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CD4011BPWR

Public Made by Adom

by adom

Texas Instruments Gates, TSSOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs cd4011bpwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers cd4011bpwr: viewers · Ray 2mo ago
cd4011bpwr-etched.fit.json cd4011bpwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
cd4011bpwr-etched.glb cd4011bpwr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray 15d ago
cd4011bpwr-etched.step cd4011bpwr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray 15d ago
cd4011bpwr.glb Publish 0.1.0 · Ray 2mo ago
cd4011bpwr.kicad_mod Publish 0.1.0 · Ray 2mo ago
cd4011bpwr.kicad_sym Publish 0.1.0 · Ray 2mo ago
cd4011bpwr.lbr Publish 0.1.0 · Ray 2mo ago
cd4011bpwr.step Publish 0.1.0 · Ray 2mo ago
package.json Publish 0.2.0 · Ray 2mo ago
page.json cd4011bpwr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray 15d ago
README.md cd4011bpwr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago

CD4011BPWR

Texas Instruments · Gates · TSSOP-14

CD4011BPWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Gate 1 input A. CMOS logic input, VIH = 3.5 V min at VDD = 5 V. Protected by internal CMOS clamp network to VDD and VSS.
2 1B input Gate 1 input B. CMOS logic input, VIH = 3.5 V min at VDD = 5 V. Protected by internal CMOS clamp network to VDD and VSS.
3 1Y output Gate 1 output, Y = NAND(1A, 1B). Buffered CMOS output; IOL/IOH typ 1 mA at VDD = 5 V.
4 2Y output Gate 2 output, Y = NAND(2A, 2B). Buffered CMOS output; IOL/IOH typ 1 mA at VDD = 5 V.
5 2A input Gate 2 input A. CMOS logic input, VIH = 3.5 V min at VDD = 5 V.
6 2B input Gate 2 input B. CMOS logic input, VIH = 3.5 V min at VDD = 5 V.
7 VSS power_in Negative supply / ground reference. Normally tied to 0 V. All input and output voltages are referenced to this pin.
8 3A input Gate 3 input A. CMOS logic input, VIH = 3.5 V min at VDD = 5 V.
9 3B input Gate 3 input B. CMOS logic input, VIH = 3.5 V min at VDD = 5 V.
10 3Y output Gate 3 output, Y = NAND(3A, 3B). Buffered CMOS output; IOL/IOH typ 1 mA at VDD = 5 V.
11 4Y output Gate 4 output, Y = NAND(4A, 4B). Buffered CMOS output; IOL/IOH typ 1 mA at VDD = 5 V.
12 4A input Gate 4 input A. CMOS logic input, VIH = 3.5 V min at VDD = 5 V.
13 4B input Gate 4 input B. CMOS logic input, VIH = 3.5 V min at VDD = 5 V.
14 VDD power_in Positive supply. Recommended operating range 3 V to 18 V (absolute maximum -0.5 V to +20 V referenced to VSS). Bypass to VSS with a local decoupling capacitor.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-14
Category Logic
Pins 14

Ordering variants

Same part, different packaging or reel option.

  • CD4011BPWR
  • CD4011BPWRG4
  • CD4011BPWRE
  • CD4011BPWREE4
  • CD4011BPWRF
  • CD4011BPWRF3A
  • CD4011BPWRM
  • CD4011BPWRM96
  • CD4011BPWRME4
  • CD4011BPWRM96E4
  • CD4011BPWRMT
  • CD4011BPWRNSR

CAD (KiCad official)

  • Symbol: CD4011BPWR
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4011bpwr-etched.step / cd4011bpwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4011bpwr.step / cd4011bpwr.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
cd4011bpwr.step 194 KB You want the bare part, or you mark your own boards.
cd4011bpwr-etched.step 2.3 MB You want the part with CD4011BPWR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 587 faces against 237 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (23 pp, sha256 92d82fa35555e4e4, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF