component

CD4011BM-MS

Public Made by Adom

by adom

MSKSEMI Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogiccd4011bm-msfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 15h ago
viewers cd4011bm-ms: viewers · Ray 15h ago
cd4011bm-ms-etched.glb Publish 0.1.0 · Ray 15h ago
cd4011bm-ms-etched.step cd4011bm-ms: factory component page (tier=lcsc) · Ray 15h ago
cd4011bm-ms-hero.glb cd4011bm-ms: hero GLB from the etched model (keeps the MPN mark) · Ray 15h ago
cd4011bm-ms-hero.overlay.json Publish 0.1.0 · Ray 15h ago
cd4011bm-ms.glb Publish 0.1.0 · Ray 15h ago
cd4011bm-ms.kicad_mod Publish 0.1.0 · Ray 15h ago
cd4011bm-ms.kicad_sym Publish 0.1.0 · Ray 15h ago
cd4011bm-ms.lbr Publish 0.1.0 · Ray 15h ago
cd4011bm-ms.step Publish 0.1.0 · Ray 15h ago
package.json Publish 0.1.0 · Ray 15h ago
page.json Set visibility: public · Ray 15h ago
README.md Publish 0.1.0 · Ray 15h ago

CD4011BM-MS

MSKSEMI · Logic Gates · SOP-14

CD4011BM-MS from MSKSEMI, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A1 input Input A of NAND gate 1; recommended input voltage is 0 to VDD V, with absolute input limits of VSS-0.5 V to VDD+0.5 V.
2 B1 input Input B of NAND gate 1; recommended input voltage is 0 to VDD V, with absolute input limits of VSS-0.5 V to VDD+0.5 V.
3 Y1 output Output Y of NAND gate 1; the datasheet gives VOH/VOL and source/sink limits (IOH and IOL) for this output.
4 Y2 output Output Y of NAND gate 2; the datasheet gives VOH/VOL and source/sink limits (IOH and IOL) for this output.
5 A2 input Input A of NAND gate 2; recommended input voltage is 0 to VDD V, with absolute input limits of VSS-0.5 V to VDD+0.5 V.
6 B2 input Input B of NAND gate 2; recommended input voltage is 0 to VDD V, with absolute input limits of VSS-0.5 V to VDD+0.5 V.
7 VSS power_in Ground/negative supply reference for the device; all voltage limits are referenced to VSS.
8 A3 input Input A of NAND gate 3; recommended input voltage is 0 to VDD V, with absolute input limits of VSS-0.5 V to VDD+0.5 V.
9 B3 input Input B of NAND gate 3; recommended input voltage is 0 to VDD V, with absolute input limits of VSS-0.5 V to VDD+0.5 V.
10 Y3 output Output Y of NAND gate 3; the datasheet gives VOH/VOL and source/sink limits (IOH and IOL) for this output.
11 Y4 output Output Y of NAND gate 4; the datasheet gives VOH/VOL and source/sink limits (IOH and IOL) for this output.
12 A4 input Input A of NAND gate 4; recommended input voltage is 0 to VDD V, with absolute input limits of VSS-0.5 V to VDD+0.5 V.
13 B4 input Input B of NAND gate 4; recommended input voltage is 0 to VDD V, with absolute input limits of VSS-0.5 V to VDD+0.5 V.
14 VDD power_in Positive supply; recommended operating voltage is 2.5 V to 15 V, with an absolute maximum rating of -0.5 V to 18 V.

Key specifications

Parameter Value
Manufacturer MSKSEMI
Package SOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD 2.5 15 V 4
Operating temperature TA 0 60 ℃ 4
Input/output voltage VIN, VOUT 0 V printed max is VDD 4
Supply voltage VDD -0.5 18 V 3
Input voltage VIN -0.5 V printed as -0.5+VSS-VDD+0.5 V 3
Power dissipation PD 500 mW 3
Operating temperature TA 0 70 ℃ 3
Storage temperature TS -65 150 ℃ 3
Lead soldering temperature TW 260 ℃ 10s 3
High-level input voltage VIH 3.5 V /IO/≤1uA, Vo=0.5V, VDD=5V 4
High-level input voltage VIH 7 V /IO/≤1uA, Vo=1V, VDD=10V 4
High-level input voltage VIH 11 V /IO/≤1uA, Vo=1.5V, VDD=15V 4
Low-level input voltage VIL 1.5 V /IO/≤1uA, Vo=4.5V, VDD=5V 4
Low-level input voltage VIL 3 V /IO/≤1uA, Vo=9V, VDD=10V 4
Low-level input voltage VIL 4 V /IO/≤1uA, Vo=13.5V, VDD=15V 4
High-level output voltage VOH 4.95 V /IOUT/<1uA, VDD=5V 4
High-level output voltage VOH 9.95 V /IOUT/<1uA, VDD=10V 4
High-level output voltage VOH 14.95 V /IOUT/<1uA, VDD=15V 4
Low-level output voltage VOL 0.05 V /IOUT/<1uA, VDD=5V 4
Input current IIN 0.01 1 uA VIN=VDD or VSS, VDD=15V 4
High-level output current IOH -1 -0.5 mA Vo=4.6V, VDD=5V 4
High-level output current IOH -2.1 -1.3 mA Vo=9.5V, VDD=10V 4
High-level output current IOH -8 -3.4 mA Vo=13.5V, VDD=15V 4
Low-level output current IOL 0.5 2.2 mA Vo=0.4V, VDD=5V 4
Low-level output current IOL 1.3 5.1 mA Vo=0.5V, VDD=10V 4
Low-level output current IOL 3.4 19 mA Vo=1.5V, VDD=15V 4
Quiescent supply current IDD 0.1 4 uA VIN=VDD or VSS, VDD=5V 4
Quiescent supply current IDD 0.1 5 uA VIN=VDD or VSS, VDD=10V 4
Quiescent supply current IDD 0.1 6 uA VIN=VDD or VSS, VDD=15V 4
Maximum propagation delay time tPHL tPHL 62 ns A,B to Y; Ta=25℃, RL=197k, CL=51pF; VDD=5V 4
Maximum propagation delay time tPLH tPLH 55 ns A,B to Y; Ta=25℃, RL=197k, CL=51pF; VDD=5V 4
Maximum propagation delay time tPHL tPHL 35 ns A,B to Y; Ta=25℃, RL=197k, CL=51pF; VDD=10V 4
Maximum propagation delay time tPLH tPLH 35 ns A,B to Y; Ta=25℃, RL=197k, CL=51pF; VDD=10V 4
Maximum propagation delay time tPHL tPHL 30 ns A,B to Y; Ta=25℃, RL=197k, CL=51pF; VDD=15V 4
Maximum propagation delay time tPLH tPLH 28 ns A,B to Y; Ta=25℃, RL=197k, CL=51pF; VDD=15V 4

CAD (KiCad official)

  • Symbol: CD4011BM-MS
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4011bm-ms-etched.step / cd4011bm-ms-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4011bm-ms.step / cd4011bm-ms.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: MSKSEMI datasheet (8 pp, sha256 434699158e8ca1ee, retrieved 2026-10-27, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus off (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF