# CD40106BM-JSM

**JSMSEMI** · Flip Flops · SOP-14

CD40106BM-JSM from JSMSEMI, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Schmitt-trigger inverter 1 input; accepts 0 V to VDD; hysteresis thresholds VT− / VT+ defined vs. VDD (e.g. 0.7 V / 2.0 V at VDD=5 V); input leakage ±10⁻⁵ µA typ at VDD=15 V. |
| 2 | 1Y | output | Schmitt-trigger inverter 1 output (active-low of 1A); CMOS push-pull; VOL ≤0.05 V, VOH ≥14.95 V at VDD=15 V, IOH/IOL ±6.8 mA max at VDD=15 V. |
| 3 | 2A | input | Schmitt-trigger inverter 2 input; same thresholds and leakage spec as pin 1. |
| 4 | 2Y | output | Schmitt-trigger inverter 2 output (active-low of 2A); same drive spec as pin 2. |
| 5 | 3A | input | Schmitt-trigger inverter 3 input; same thresholds and leakage spec as pin 1. |
| 6 | 3Y | output | Schmitt-trigger inverter 3 output (active-low of 3A); same drive spec as pin 2. |
| 7 | VSS | power_in | Ground reference (0 V); VSS=0 V per datasheet Note 2; all electrical parameters referenced to this rail. |
| 8 | 4Y | output | Schmitt-trigger inverter 4 output (active-low of 4A); same drive spec as pin 2. |
| 9 | 4A | input | Schmitt-trigger inverter 4 input; same thresholds and leakage spec as pin 1. |
| 10 | 5Y | output | Schmitt-trigger inverter 5 output (active-low of 5A); same drive spec as pin 2. |
| 11 | 5A | input | Schmitt-trigger inverter 5 input; same thresholds and leakage spec as pin 1. |
| 12 | 6Y | output | Schmitt-trigger inverter 6 output (active-low of 6A); same drive spec as pin 2. |
| 13 | 6A | input | Schmitt-trigger inverter 6 input; same thresholds and leakage spec as pin 1. |
| 14 | VDD | power_in | Positive supply rail; recommended 5-15 VDC (Note 2); absolute maximum −0.5 V to +18 V; SOP package rated 500 mW max power dissipation. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | JSMSEMI |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |

## CAD (KiCad official)

- Symbol: `CD40106BM-JSM`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files: `cd40106bm-jsm-etched.step` / `cd40106bm-jsm-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd40106bm-jsm.step` / `cd40106bm-jsm.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [JSMSEMI datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590917120010510336) (7 pp, sha256 `74a57514115e937b`, retrieved 2026-09-22, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-sonnet-4-6` (vision), consensus `claude-opus-4-7` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cd40106bm-jsm-datasheet.pdf)