component
CD40106BM-JSM
Public Made by Adomby adom
JSMSEMI Flip Flops, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+51@@ -0,0 +1,51 @@+# CD40106BM-JSM++**JSMSEMI** · Flip Flops · SOP-14++CD40106BM-JSM from JSMSEMI, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1A | input | Schmitt-trigger inverter 1 input; accepts 0 V to VDD; hysteresis thresholds VT− / VT+ defined vs. VDD (e.g. 0.7 V / 2.0 V at VDD=5 V); input leakage ±10⁻⁵ µA typ at VDD=15 V. |+| 2 | 1Y | output | Schmitt-trigger inverter 1 output (active-low of 1A); CMOS push-pull; VOL ≤0.05 V, VOH ≥14.95 V at VDD=15 V, IOH/IOL ±6.8 mA max at VDD=15 V. |+| 3 | 2A | input | Schmitt-trigger inverter 2 input; same thresholds and leakage spec as pin 1. |+| 4 | 2Y | output | Schmitt-trigger inverter 2 output (active-low of 2A); same drive spec as pin 2. |+| 5 | 3A | input | Schmitt-trigger inverter 3 input; same thresholds and leakage spec as pin 1. |+| 6 | 3Y | output | Schmitt-trigger inverter 3 output (active-low of 3A); same drive spec as pin 2. |+| 7 | VSS | power_in | Ground reference (0 V); VSS=0 V per datasheet Note 2; all electrical parameters referenced to this rail. |+| 8 | 4Y | output | Schmitt-trigger inverter 4 output (active-low of 4A); same drive spec as pin 2. |+| 9 | 4A | input | Schmitt-trigger inverter 4 input; same thresholds and leakage spec as pin 1. |+| 10 | 5Y | output | Schmitt-trigger inverter 5 output (active-low of 5A); same drive spec as pin 2. |+| 11 | 5A | input | Schmitt-trigger inverter 5 input; same thresholds and leakage spec as pin 1. |+| 12 | 6Y | output | Schmitt-trigger inverter 6 output (active-low of 6A); same drive spec as pin 2. |+| 13 | 6A | input | Schmitt-trigger inverter 6 input; same thresholds and leakage spec as pin 1. |+| 14 | VDD | power_in | Positive supply rail; recommended 5-15 VDC (Note 2); absolute maximum −0.5 V to +18 V; SOP package rated 500 mW max power dissipation. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | JSMSEMI |+| Package | SOP-14 |+| Category | Logic |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `CD40106BM-JSM`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOP-14 (KiCad packages3D, STEP)+- 3D model files: `cd40106bm-jsm-etched.step` / `cd40106bm-jsm-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd40106bm-jsm.step` / `cd40106bm-jsm.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [JSMSEMI datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590917120010510336) (7 pp, sha256 `74a57514115e937b`, retrieved 2026-09-22, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-sonnet-4-6` (vision), consensus `claude-opus-4-7` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd40106bm-jsm-datasheet.pdf)
page.jsonadded+179@@ -0,0 +1,179 @@+{+ "slug": "cd40106bm-jsm",+ "version": "0.1.0",+ "type": "component",+ "description": "JSMSEMI Flip Flops, SOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "cd40106bm-jsm",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cd40106bm-jsm.kicad_sym",+ "cd40106bm-jsm.kicad_mod",+ "cd40106bm-jsm.glb",+ "cd40106bm-jsm.step",+ "cd40106bm-jsm.lbr",+ "docs/hero.png",+ "docs/cd40106bm-jsm-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "CD40106BM-JSM",+ "manufacturer": "JSMSEMI",+ "package": "SOP-14",+ "pin_count": 14,+ "category": "Logic",+ "subcategory": "Flip Flops",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590917120010510336",+ "parts": {+ "symbol": "cd40106bm-jsm.kicad_sym",+ "footprint": "cd40106bm-jsm.kicad_mod",+ "model_3d": "cd40106bm-jsm-etched.glb",+ "model_3d_plain": "cd40106bm-jsm.glb",+ "model_3d_step": "cd40106bm-jsm-etched.step",+ "model_3d_step_plain": "cd40106bm-jsm.step",+ "lbr": "cd40106bm-jsm.lbr"+ },+ "distributor_links": {+ "lcsc": "C22376098"+ },+ "pins": [+ {+ "number": "1",+ "name": "1A",+ "type": "input",+ "description": "Schmitt-trigger inverter 1 input; accepts 0 V to VDD; hysteresis thresholds VT− / VT+ defined vs. VDD (e.g. 0.7 V / 2.0 V at VDD=5 V); input leakage ±10⁻⁵ µA typ at VDD=15 V."+ },+ {+ "number": "2",+ "name": "1Y",+ "type": "output",+ "description": "Schmitt-trigger inverter 1 output (active-low of 1A); CMOS push-pull; VOL ≤0.05 V, VOH ≥14.95 V at VDD=15 V, IOH/IOL ±6.8 mA max at VDD=15 V."+ },+ {+ "number": "3",+ "name": "2A",+ "type": "input",+ "description": "Schmitt-trigger inverter 2 input; same thresholds and leakage spec as pin 1."+ },+ {+ "number": "4",+ "name": "2Y",+ "type": "output",+ "description": "Schmitt-trigger inverter 2 output (active-low of 2A); same drive spec as pin 2."+ },+ {+ "number": "5",+ "name": "3A",+ "type": "input",+ "description": "Schmitt-trigger inverter 3 input; same thresholds and leakage spec as pin 1."+ },+ {+ "number": "6",+ "name": "3Y",+ "type": "output",+ "description": "Schmitt-trigger inverter 3 output (active-low of 3A); same drive spec as pin 2."+ },+ {+ "number": "7",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference (0 V); VSS=0 V per datasheet Note 2; all electrical parameters referenced to this rail."+ },+ {+ "number": "8",+ "name": "4Y",+ "type": "output",+ "description": "Schmitt-trigger inverter 4 output (active-low of 4A); same drive spec as pin 2."+ },+ {+ "number": "9",+ "name": "4A",+ "type": "input",+ "description": "Schmitt-trigger inverter 4 input; same thresholds and leakage spec as pin 1."+ },+ {+ "number": "10",+ "name": "5Y",+ "type": "output",+ "description": "Schmitt-trigger inverter 5 output (active-low of 5A); same drive spec as pin 2."+ },+ {+ "number": "11",+ "name": "5A",+ "type": "input",+ "description": "Schmitt-trigger inverter 5 input; same thresholds and leakage spec as pin 1."+ },+ {+ "number": "12",+ "name": "6Y",+ "type": "output",+ "description": "Schmitt-trigger inverter 6 output (active-low of 6A); same drive spec as pin 2."+ },+ {+ "number": "13",+ "name": "6A",+ "type": "input",+ "description": "Schmitt-trigger inverter 6 input; same thresholds and leakage spec as pin 1."+ },+ {+ "number": "14",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply rail; recommended 5-15 VDC (Note 2); absolute maximum −0.5 V to +18 V; SOP package rated 500 mW max power dissipation."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-sonnet-4-6",+ "primary_mode": "vision",+ "consensus_model": "claude-opus-4-7",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "vision extraction: provenance cannot be text-verified; needs consensus"+ ],+ "pages_sent": 7,+ "cost_usd": 0.1857,+ "at": "2026-09-22T11:00:14"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590917120010510336",+ "pages": 7,+ "sha256": "74a57514115e937b",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}