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CD40103BPW

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Texas Instruments Counters, Dividers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD40103BPW

Texas Instruments · Counters, Dividers · TSSOP-16

CD40103BPW from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLOCK input Clock input; the counter decrements on each positive clock transition, with a maximum clock input frequency of 0.7 MHz at 5 V (min), 1.8 MHz at 10 V, and 2.4 MHz at 15 V.
2 CLR input Active-low asynchronous clear; when low the counter is cleared to its maximum count (255 for the CD40103B) regardless of the other inputs.
3 CI/CE input Active-low carry-in/counter enable; counting is inhibited when this input is high, and it is used to cascade counters.
4 J0 input Jam (preset) data input J0, the least significant bit of the 8-bit binary word for the CD40103B.
5 J1 input Jam (preset) data input J1 for the CD40103B 8-bit binary word.
6 J2 input Jam (preset) data input J2 for the CD40103B 8-bit binary word.
7 J3 input Jam (preset) data input J3 for the CD40103B 8-bit binary word.
8 VSS power_in Ground (VSS) supply terminal; the supply voltage VDD is referenced to it.
9 APE input Active-low asynchronous preset enable; when low, the JAM data is forced asynchronously into the counter regardless of SPE, CI/CE or CLOCK.
10 J4 input Jam (preset) data input J4 for the CD40103B 8-bit binary word.
11 J5 input Jam (preset) data input J5 for the CD40103B 8-bit binary word.
12 J6 input Jam (preset) data input J6 for the CD40103B 8-bit binary word.
13 J7 input Jam (preset) data input J7, the most significant bit of the CD40103B 8-bit binary word.
14 CO/ZD output Active-low carry-out/zero-detect output; goes low when the count reaches zero while CI/CE is low and stays low for one full clock period.
15 SPE input Active-low synchronous preset enable; when low, the JAM data is clocked into the counter on the next positive clock transition.
16 VDD power_in Positive supply voltage; recommended range is 3 V to 18 V, and the absolute maximum is -0.5 V to +20 V referenced to VSS.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: CD40103BPW
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: cd40103bpw-etched.step / cd40103bpw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd40103bpw.step / cd40103bpw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (21 pp, sha256 1a982876aec1d075, retrieved 2026-10-07, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF