CC6902SO-20A

{
  "schema_version": 1,
  "type": "component",
  "slug": "cc6902so-20a",
  "title": "CC6902SO-20A",
  "brief": "Cross chip Current Sensors, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.2.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "sensor",
    "cc6902so-20a"
  ],
  "component": {
    "mpn": "CC6902SO-20A",
    "manufacturer": "Cross chip",
    "package": "SOP-8",
    "pin_count": 8,
    "category": "Sensor",
    "subcategory": "Current Sensors",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/42da73268b22eb62a84fa1db02426768.pdf",
    "parts": {
      "symbol": "cc6902so-20a.kicad_sym",
      "footprint": "cc6902so-20a.kicad_mod",
      "model_3d": "cc6902so-20a-etched.glb",
      "model_3d_plain": "cc6902so-20a.glb",
      "model_3d_step": "cc6902so-20a-etched.step",
      "model_3d_step_plain": "cc6902so-20a.step",
      "lbr": "cc6902so-20a.lbr"
    },
    "distributor_links": {
      "lcsc": "C350866"
    },
    "pins": [
      {
        "number": "1",
        "name": "IP+",
        "type": "passive",
        "description": "Positive terminal of the primary sampled-current conductor. Pins 1 and 2 are tied together internally and must be paralleled on the PCB to carry the sensed current into the die's integrated low-impedance conductor."
      },
      {
        "number": "2",
        "name": "IP+",
        "type": "passive",
        "description": "Second positive terminal of the primary sampled-current conductor, internally common with pin 1. Both pins must be paralleled for full current-handling capability."
      },
      {
        "number": "3",
        "name": "IP-",
        "type": "passive",
        "description": "Negative terminal of the primary sampled-current conductor. Pins 3 and 4 are internally common and must be paralleled on the PCB to complete the sensed-current return path."
      },
      {
        "number": "4",
        "name": "IP-",
        "type": "passive",
        "description": "Second negative terminal of the primary sampled-current conductor, internally common with pin 3. Both pins must be paralleled for full current-handling capability."
      },
      {
        "number": "5",
        "name": "GND",
        "type": "power_in",
        "description": "Signal-side ground reference for the Hall front-end, output amplifier, and VCC decoupling."
      },
      {
        "number": "6",
        "name": "NC",
        "type": "unconnected",
        "description": "No internal connection. Must be left floating (需悬空); do not connect to any net or plane."
      },
      {
        "number": "7",
        "name": "OUT",
        "type": "output",
        "description": "Ratiometric single-ended analog output. Quiescent output is 50% VCC with no field; for the -20A variant, sensitivity is 100 mV/A and the output swings linearly across ~0.5 V to 4.5 V (at VCC = 5 V) with the primary current through IP+/IP-."
      },
      {
        "number": "8",
        "name": "VCC",
        "type": "power_in",
        "description": "Signal-side supply input, typically 5 V. Bypass locally to GND (pin 5) with a low-ESR ceramic capacitor for chopper-noise filtering."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/42da73268b22eb62a84fa1db02426768.pdf",
        "pages": 3,
        "sha256": "bd4558c14185b3b8",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "pin1": {
      "pad": "1",
      "at": [
        -2.475,
        -1.905
      ],
      "corner": "top-left",
      "source": "silk-marker",
      "derived_from": "SOIC-8_3.9x4.9mm_P1.27mm@sha256:074ecb2092b24fa4",
      "mark": "drawn"
    }
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Cross chip",
      "Package": "SOP-8",
      "Category": "Sensor",
      "Pins": "8"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "cc6902so-20a"
  ],
  "discovery_pitch": "CC6902SO-20A (Cross chip) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cc6902so-20a.kicad_sym",
    "cc6902so-20a.kicad_mod",
    "cc6902so-20a.glb",
    "cc6902so-20a.step",
    "cc6902so-20a-etched.step",
    "cc6902so-20a.lbr",
    "docs/hero.png",
    "docs/cc6902so-20a-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "variants": [
    {
      "mpn": "CC6902SO-20A",
      "kind": "packaging"
    }
  ],
  "updated_at": "2026-09-24T18:34:45.938Z"
}