component

CC6902SO-20A

Public Made by Adom

by adom

Cross chip Current Sensors, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs cc6902so-20a: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
cc6902so-20a-etched.fit.json cc6902so-20a: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
cc6902so-20a-etched.glb cc6902so-20a: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
cc6902so-20a-etched.step cc6902so-20a: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
cc6902so-20a.glb Publish 0.1.0 · Ray 1mo ago
cc6902so-20a.kicad_mod Publish 0.1.0 · Ray 1mo ago
cc6902so-20a.kicad_sym Publish 0.1.0 · Ray 1mo ago
cc6902so-20a.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect and oval pad as a SQUARE EAGLE smd; this carries the real pad shape across (0 -> 8 rounded pads) and stops dropping geometry drawn on KiCad User.N layers. Attributes, connects, pads and the pin-1 marker are gated against decreasing and are unchanged. · Ray 1mo ago
cc6902so-20a.step Publish 0.1.0 · Ray 1mo ago
package.json Publish 0.2.0 · Ray 1mo ago
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
page.json Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout") · Ray 11d ago
README.md cc6902so-20a: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 18d ago

CC6902SO-20A

Cross chip · Current Sensors · SOP-8

CC6902SO-20A from Cross chip, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IP+ passive Positive terminal of the primary sampled-current conductor. Pins 1 and 2 are tied together internally and must be paralleled on the PCB to carry the sensed current into the die's integrated low-impedance conductor.
2 IP+ passive Second positive terminal of the primary sampled-current conductor, internally common with pin 1. Both pins must be paralleled for full current-handling capability.
3 IP- passive Negative terminal of the primary sampled-current conductor. Pins 3 and 4 are internally common and must be paralleled on the PCB to complete the sensed-current return path.
4 IP- passive Second negative terminal of the primary sampled-current conductor, internally common with pin 3. Both pins must be paralleled for full current-handling capability.
5 GND power_in Signal-side ground reference for the Hall front-end, output amplifier, and VCC decoupling.
6 NC unconnected No internal connection. Must be left floating (需悬空); do not connect to any net or plane.
7 OUT output Ratiometric single-ended analog output. Quiescent output is 50% VCC with no field; for the -20A variant, sensitivity is 100 mV/A and the output swings linearly across ~0.5 V to 4.5 V (at VCC = 5 V) with the primary current through IP+/IP-.
8 VCC power_in Signal-side supply input, typically 5 V. Bypass locally to GND (pin 5) with a low-ESR ceramic capacitor for chopper-noise filtering.

Key specifications

Parameter Value
Manufacturer Cross chip
Package SOP-8
Category Sensor
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • CC6902SO-20A

CAD (KiCad official)

  • Symbol: CC6902SO-20A
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: cc6902so-20a-etched.step / cc6902so-20a-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cc6902so-20a.step / cc6902so-20a.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
cc6902so-20a.step 122 KB You want the bare part, or you mark your own boards.
cc6902so-20a-etched.step 2.8 MB You want the part with CC6902SO-20A already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 649 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cross chip datasheet (3 pp, sha256 bd4558c14185b3b8, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF