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CBM708RAS8

Public Made by Adom

by adom

Corebai Microelectronics Supervisor and Reset ICs, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs cbm708ras8: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers cbm708ras8: viewers · Ray
cbm708ras8-etched.fit.json cbm708ras8: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cbm708ras8-etched.glb cbm708ras8: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cbm708ras8-etched.step cbm708ras8: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cbm708ras8.glb Publish 0.1.0 · Ray
cbm708ras8.kicad_mod Publish 0.1.0 · Ray
cbm708ras8.kicad_sym Publish 0.1.0 · Ray
cbm708ras8.lbr Publish 0.1.0 · Ray
cbm708ras8.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json cbm708ras8: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md cbm708ras8: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray

CBM708RAS8

Corebai Microelectronics · Supervisor and Reset ICs · SOIC-8

CBM708RAS8 from Corebai Microelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MR input Manual Reset Input (active low, overline MR). Taking this pin below 0.6 V generates a RESET/RESET pulse. Internally debounced with a 70 µA pull-up (25-250 µA), so the pin may be left floating or driven by a switch, TTL, or CMOS logic.
2 VCC power_in Power Supply Input. Operating range 2.70-5.5 V for the 708R variant (absolute max −0.3 to +6 V). Place a 0.1 µF decoupling capacitor between VCC and GND. Quiescent supply current ~100 µA typ.
3 GND power_in Ground reference for all signals (0 V).
4 PFI input Power-Fail Input. Noninverting input to the internal 1.25 V power-fail comparator. When PFI drops below 1.25 V (typ), PFO goes low. Input current ±25 nA max. If unused, tie PFI to GND.
5 PFO output Power-Fail Output (active low, overline PFO). Open push-pull output from the 1.25 V comparator; goes low whenever PFI < 1.25 V. VOH ≥ 0.8×VCC (ISOURCE = 500 µA), VOL ≤ 0.3 V (ISINK = 1.2 mA).
6 NC unconnected No Connect. Not internally bonded; leave floating or tie to GND. (Replaces the WDI watchdog input found on the CBM706x parts.)
7 RESET output Active-low Reset Output (overline RESET). Asserts low for 200 ms (typ) whenever VCC drops below the 2.63 V reset threshold or MR is pulled low; remains low until 200 ms after VCC recovers and MR is released. Guaranteed valid with VCC as low as 1 V. VOH ≥ 0.8×VCC @ ISOURCE = 500 µA; VOL ≤ 0.3 V @ ISINK = 500 µA.
8 RESET output Active-high Reset Output (non-inverted). Logical inverse of pin 7's RESET, suitable for systems needing an active-high reset. Same drive levels as the active-low RESET output.

Key specifications

Parameter Value
Manufacturer Corebai Microelectronics
Package SOIC-8
Category PMIC
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • CBM708RAS8

CAD (KiCad official)

  • Symbol: CBM708RAS8
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: cbm708ras8-etched.step / cbm708ras8-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cbm708ras8.step / cbm708ras8.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Corebai Microelectronics datasheet (19 pp, sha256 c45131be953a4993, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF