CAV24C32YE-GT3 from onsemi, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	A0	input	Device address input that must match the slave address bit A0; hard-wired HIGH or LOW and pulled LOW internally when left floating.
2	A1	input	Device address input that must match the slave address bit A1; hard-wired HIGH or LOW and pulled LOW internally when left floating.
3	A2	input	Device address input that must match the slave address bit A2; hard-wired HIGH or LOW and pulled LOW internally when left floating.
4	VSS	power_in	Ground.
5	SDA	bidirectional	Serial data input/output that is open drain when transmitting, with data acquired on the positive edge and delivered on the negative edge of SCL.
6	SCL	input	Serial clock input that accepts the clock signal generated by the master.
7	WP	input	Write protect input that inhibits all write operations when pulled HIGH and is pulled LOW internally when left floating.
8	VCC	power_in	Power supply, 2.5 V to 5.5 V.

Key specifications

Parameter	Value
Manufacturer	onsemi
Package	TSSOP-8
Category	Memory
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Max	Unit	Conditions	Page
Storage Temperature		-65	150	°C		2
Voltage on any Pin with Respect to Ground		-0.5	6.5	V		2
Supply Voltage	VCC	2.5	5.5	V		2
Operating Temperature	TA	-40	125	°C		2
Endurance	NEND	1e+06		Program/Erase Cycles	Page Mode, VCC = 5 V, 25°C (Note 3)	2
Data Retention	TDR	100		Years		2
Read Current	ICCR		1	mA	Read, fSCL = 400 kHz	2
Write Current	ICCW		2	mA	Write, fSCL = 400 kHz	2
Standby Current	ISB		5	µA	All I/O Pins at GND or VCC; TA = −40°C to +125°C	2
I/O Pin Leakage	IL		2	µA	Pin at GND or VCC	2
Input Low Voltage	VIL	-0.5		V		2
Input Low Voltage	VIL		0.3	x VCC		2
Input High Voltage	VIH	0.7		x VCC	A0, A1, A2 and WP	2
Input High Voltage	VIH		5.5	V	SCL and SDA	2
Output Low Voltage	VOL		0.4	V	VCC > 2.5 V, IOL = 3 mA	2
SDA I/O Pin Capacitance	CIN		8	pF	VIN = 0 V, TA = 25°C, VCC = 5.0 V	3
Input Capacitance (other pins)	CIN		6	pF	VIN = 0 V, TA = 25°C, VCC = 5.0 V	3
WP Input Current	IWP		130	µA	VIN < VIH, VCC = 5.5 V	3
WP Input Current	IWP		120	µA	VIN < VIH, VCC = 3.3 V	3
WP Input Current	IWP		80	µA	VIN < VIH, VCC = 2.5 V	3
WP Input Current	IWP		2	µA	VIN < VIH	3
Address Input Current (A0, A1, A2)	IA		50	µA	VIN < VIH, VCC = 5.5 V	3
Address Input Current (A0, A1, A2)	IA		35	µA	VIN < VIH, VCC = 3.3 V	3
Address Input Current (A0, A1, A2)	IA		25	µA	VIN < VIH, VCC = 2.5 V	3
Address Input Current (A0, A1, A2)	IA		2	µA	VIN > VIH	3
Clock Frequency	FSCL		100	kHz	Standard mode	3
Clock Frequency	FSCL		400	kHz	Fast mode	3
START Condition Hold Time	tHD:STA	4		µs	Standard mode	3
START Condition Hold Time	tHD:STA	0.6		µs	Fast mode	3
Low Period of SCL Clock	tLOW	4.7		µs	Standard mode	3
Low Period of SCL Clock	tLOW	1.3		µs	Fast mode	3
High Period of SCL Clock	tHIGH	4		µs	Standard mode	3
High Period of SCL Clock	tHIGH	0.6		µs	Fast mode	3
START Condition Setup Time	tSU:STA	4.7		µs	Standard mode	3
START Condition Setup Time	tSU:STA	0.6		µs	Fast mode	3
Data In Hold Time	tHD:DAT	0		µs	Standard and Fast mode	3
Data In Setup Time	tSU:DAT	250		ns	Standard mode	3
Data In Setup Time	tSU:DAT	100		ns	Fast mode	3
SDA and SCL Rise Time	tR		1000	ns	Standard mode	3
SDA and SCL Rise Time	tR		300	ns	Fast mode	3
SDA and SCL Fall Time	tF		300	ns	Standard and Fast mode	3
STOP Condition Setup Time	tSU:STO	4		µs	Standard mode	3
STOP Condition Setup Time	tSU:STO	0.6		µs	Fast mode	3
Bus Free Time Between STOP and START	tBUF	4.7		µs	Standard mode	3
Bus Free Time Between STOP and START	tBUF	1.3		µs	Fast mode	3
SCL Low to Data Out Valid	tAA		3.5	µs	Standard mode	3
SCL Low to Data Out Valid	tAA		0.9	µs	Fast mode	3
Data Out Hold Time	tDH	100		ns	Standard and Fast mode	3
Noise Pulse Filtered at SCL and SDA Inputs	Ti		100	ns	Standard and Fast mode	3
WP Setup Time	tSU:WP	0		µs	Standard and Fast mode	3
WP Hold Time	tHD:WP	2.5		µs	Standard and Fast mode	3
Write Cycle Time	tWR		5	ms	Standard and Fast mode	3
Power-up to Ready Mode	tPU		1	ms	Standard and Fast mode	3

CAD (KiCad official)

Symbol: CAV24C32YE-GT3
Footprint: Package_SO:TSSOP-8_4.4x3mm_P0.65mm
3D model: TSSOP-8 (KiCad packages3D, STEP)
3D model files: cav24c32ye-gt3-etched.step / cav24c32ye-gt3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cav24c32ye-gt3.step / cav24c32ye-gt3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: onsemi datasheet (15 pp, sha256 4145e0c551c1fe57, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

CAV24C32YE-GT3

Verified CAV24C32YE-GT3

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README