component
CA-IS3762LW
Public Made by Adomby adom
Chipanalog Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
Ray
Publish 0.1.0
dca0605
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{
"slug": "ca-is3762lw",
"version": "0.1.0",
"type": "component",
"description": "Chipanalog Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"interface ics",
"ca-is3762lw",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
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"README.md",
"ca-is3762lw.kicad_sym",
"ca-is3762lw.kicad_mod",
"ca-is3762lw.glb",
"ca-is3762lw.step",
"ca-is3762lw.lbr",
"docs/hero.png",
"docs/ca-is3762lw-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"ca-is3762lw-hero.glb",
"ca-is3762lw-hero.overlay.json",
"ca-is3762lw-etched.glb"
],
"component": {
"mpn": "CA-IS3762LW",
"manufacturer": "Chipanalog",
"package": "SOIC-16-300mil",
"pin_count": 16,
"category": "Interface ICs",
"subcategory": "Digital Isolators",
"datasheet": "https://datasheet.lcsc.com/datasheet/pdf/a3d31674f5dd929b2ba9319168218955.pdf",
"parts": {
"symbol": "ca-is3762lw.kicad_sym",
"footprint": "ca-is3762lw.kicad_mod",
"model_3d": "ca-is3762lw-hero.glb",
"model_3d_plain": "ca-is3762lw-etched.glb",
"model_3d_step": "ca-is3762lw-etched.step",
"model_3d_step_plain": "ca-is3762lw.step",
"lbr": "ca-is3762lw.lbr"
},
"distributor_links": {
"lcsc": "C528660"
},
"distributor_check": {
"checked_at": "2026-11-12T08:13:07Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": null,
"status": "no match"
},
"mouser": {
"pn": null,
"status": "no match"
}
},
"pins": [
{
"number": "1",
"name": "VDDA",
"type": "power_in",
"description": "A-side supply voltage, specified from 2.375 V to 5.5 V in the recommended operating conditions, with 0.1 µF to 1 µF bypass capacitors recommended."
},
{
"number": "2",
"name": "VI1",
"type": "input",
"description": "A-side logic input of forward channel 1, a Schmitt-trigger input with VIH minimum 2.0 V and VIL maximum 0.8 V."
},
{
"number": "3",
"name": "VI2",
"type": "input",
"description": "A-side logic input of forward channel 2, a Schmitt-trigger input with VIH minimum 2.0 V and VIL maximum 0.8 V."
},
{
"number": "4",
"name": "VI3",
"type": "input",
"description": "A-side logic input of forward channel 3, a Schmitt-trigger input with VIH minimum 2.0 V and VIL maximum 0.8 V."
},
{
"number": "5",
"name": "VI4",
"type": "input",
"description": "A-side logic input of forward channel 4 on CA-IS3762, a Schmitt-trigger input with VIH minimum 2.0 V and VIL maximum 0.8 V."
},
{
"number": "6",
"name": "VO5",
"type": "output",
"description": "A-side logic output of reverse channel 5 on CA-IS3762, a rail-to-rail output with about 50 Ω output impedance."
},
{
"number": "7",
"name": "VO6",
"type": "output",
"description": "A-side logic output of reverse channel 6 on CA-IS3762, a rail-to-rail output with about 50 Ω output impedance."
},
{
"number": "8",
"name": "GNDA",
"type": "power_in",
"description": "A-side ground reference point for the A-side signals and supply."
},
{
"number": "9",
"name": "GNDB",
"type": "power_in",
"description": "B-side ground reference point, isolated from GNDA."
},
{
"number": "10",
"name": "VI6",
"type": "input",
"description": "B-side logic input of reverse channel 6 on CA-IS3762, a Schmitt-trigger input with VIH minimum 2.0 V and VIL maximum 0.8 V."
},
{
"number": "11",
"name": "VI5",
"type": "input",
"description": "B-side logic input of reverse channel 5 on CA-IS3762, a Schmitt-trigger input with VIH minimum 2.0 V and VIL maximum 0.8 V."
},
{
"number": "12",
"name": "VO4",
"type": "output",
"description": "B-side logic output of forward channel 4 on CA-IS3762, a rail-to-rail output with about 50 Ω output impedance."
},
{
"number": "13",
"name": "VO3",
"type": "output",
"description": "B-side logic output of forward channel 3, a rail-to-rail output with about 50 Ω output impedance."
},
{
"number": "14",
"name": "VO2",
"type": "output",
"description": "B-side logic output of forward channel 2, a rail-to-rail output with about 50 Ω output impedance."
},
{
"number": "15",
"name": "VO1",
"type": "output",
"description": "B-side logic output of forward channel 1, a rail-to-rail output with about 50 Ω output impedance."
},
{
"number": "16",
"name": "VDDB",
"type": "power_in",
"description": "B-side supply voltage, specified from 2.375 V to 5.5 V in the recommended operating conditions, with 0.1 µF to 1 µF bypass capacitors recommended."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The CA-IS3762 top-view diagram text on page 4 is scrambled in the extracted text, so the pin-to-func; Table 5-1 lists pins 13-15 as 'logic input/output' but the description for each says B-side logic ou; The datasheet gives one pin table for both the N (NB) and W (WB) packages, so the W variant uses the"
],
"pages_sent": 22,
"cost_usd": 0.0068,
"at": "2026-11-12T08:13:00"
},
"datasheet": {
"url": "https://datasheet.lcsc.com/datasheet/pdf/a3d31674f5dd929b2ba9319168218955.pdf",
"pages": 22,
"sha256": "adf22151c4806ef6",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 16,
"described": 16,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "ca-is3762lw.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
10.3,
10.3,
2.75
],
"zmin_mm": -0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "159663ceb2b4996b1b89d3111e4a355fc27de3e24d3570f50e5ed9086e0d73af",
"checked": "2026-11-12",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "ca-is3762lw-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
10.3,
10.3,
2.75
],
"zmin_mm": -0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "146bda6910a25eb6568f47242bfdfb9918046942555e37f4b225e19121293d29",
"checked": "2026-11-12",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
],
"package_dims": {
"package_code": "SOIC16-WB (W)",
"source_page": 19,
"D": {
"nom_mm": 10.3,
"range_mm": [
10.1,
10.5
]
},
"E1": {
"nom_mm": 7.5,
"range_mm": [
7.4,
7.6
]
},
"E": {
"nom_mm": 10.3,
"range_mm": [
10.2,
10.4
]
},
"e": {
"nom_mm": 1.27,
"range_mm": [
null,
null
]
},
"A": {
"nom_mm": 2.65,
"range_mm": [
null,
2.65
]
},
"source": "datasheet package drawing, every number found on its page (extract_pins --task dims)",
"model_check": {
"file": "ca-is3762lw.step",
"verdict": "PASS",
"reasons": [
"height and body within the datasheet's package drawing"
],
"by": "factory/package_fit.py"
}
}
}
}